From: Jiaxun Yang Date: Thu, 30 Apr 2020 16:48:02 +0000 (+0800) Subject: MIPS: Loongson64: Correct TLB type for Loongson-3 Classic X-Git-Tag: rel_imx_5.10.35_2.0.0-somdevices.0~2062^2~93 X-Git-Url: https://git.somdevices.com/?a=commitdiff_plain;h=3aed240e577ea9f5b070358766d46a0e285f0b9e;p=linux.git MIPS: Loongson64: Correct TLB type for Loongson-3 Classic Huacai just informed me that some early Loongson-3A2000 had wrong TLB type in Config0 register. That means we have to correct it via PRID. It looks like I shoudn't drop MIPS_CPU_FTLB flag in PRID case for Loongson-3 Classic. Fixes: da1bd29742b1 ("MIPS: Loongson64: Probe CPU features via CPUCFG") Signed-off-by: Jiaxun Yang Reported-by: Huacai Chen Signed-off-by: Thomas Bogendoerfer --- diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index 1736c173b242..ca2e6f1af4fe 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -1999,8 +1999,11 @@ static inline void cpu_probe_loongson(struct cpuinfo_mips *c, unsigned int cpu) * Loongson-3 Classic did not implement MIPS standard TLBINV * but implemented TLBINVF and EHINV. As currently we're only * using these two features, enable MIPS_CPU_TLBINV as well. + * + * Also some early Loongson-3A2000 had wrong TLB type in Config + * register, we correct it here. */ - c->options |= MIPS_CPU_TLBINV | MIPS_CPU_LDPTE; + c->options |= MIPS_CPU_FTLB | MIPS_CPU_TLBINV | MIPS_CPU_LDPTE; c->writecombine = _CACHE_UNCACHED_ACCELERATED; c->ases |= (MIPS_ASE_LOONGSON_MMI | MIPS_ASE_LOONGSON_CAM | MIPS_ASE_LOONGSON_EXT | MIPS_ASE_LOONGSON_EXT2);