From: Ella Feng <ella.feng@nxp.com>
Date: Wed, 25 Mar 2020 10:33:34 +0000 (+0800)
Subject: MGS-5584 arm64: imx8mn.dtsi: GPU reg format should align with soc0.
X-Git-Tag: rel_imx_5.10.35_2.0.0-somdevices.0~577^2~2^2~476
X-Git-Url: https://git.somdevices.com/?a=commitdiff_plain;h=393d111e71f67971e876f13d53b492f9616889e1;p=linux.git

MGS-5584 arm64: imx8mn.dtsi: GPU reg format should align with soc0.

GPU node is now within soc0 node, reg format need follow
“#address-cells = <1>;#size-cells = <1>;” as soc0.

Signed-off-by: Ella Feng <ella.feng@nxp.com>
---

diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
index 633cdcbf9f27..d06b251632f5 100644
--- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
@@ -1295,9 +1295,9 @@
 
 		gpu: gpu@38000000 {
 			compatible = "fsl,imx8mn-gpu", "fsl,imx6q-gpu";
-			reg = <0x0 0x38000000 0x0 0x40000>,
-			      <0x0 0x40000000 0x0 0x80000000>,
-			      <0x0 0x0 0x0 0x8000000>;
+			reg = <0x38000000 0x40000>,
+			      <0x40000000 0x80000000>,
+			      <0x0 0x8000000>;
 			reg-names = "iobase_3d", "phys_baseaddr", "contiguous_mem";
 			interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "irq_3d";