From: Shengjiu Wang <shengjiu.wang@nxp.com>
Date: Fri, 30 Aug 2019 03:24:54 +0000 (+0800)
Subject: MLK-22484: ARM64: dts: Fix mem clock for asrc
X-Git-Tag: rel_imx_4.19.35_1.1.0~88
X-Git-Url: https://git.somdevices.com/?a=commitdiff_plain;h=3306d4381ac6db3dbb08f08a6c4aaf24dcdcf528;p=linux.git

MLK-22484: ARM64: dts: Fix mem clock for asrc

The mem clock is used to access the register, if there is no
mem clock defined, we should use the ipg clock instead,
otherwise there will be kernel dump after system reboot.

[    3.010962] Kernel panic - not syncing: Asynchronous SError Interrupt
[    3.010964] CPU: 1 PID: 1 Comm: swapper/0 Not tainted 4.19.35-05057-g2134d856e6b2 #2889
[    3.010966] Hardware name: Freescale i.MX8QXP MEK (DT)
[    3.010968] Call trace:
[    3.010969]  dump_backtrace+0x0/0x178
[    3.010971]  show_stack+0x14/0x20
[    3.010972]  dump_stack+0x8c/0xac
[    3.010974]  panic+0x120/0x28c
[    3.010975]  __stack_chk_fail+0x0/0x18
[    3.010977]  arm64_serror_panic+0x74/0x80
[    3.010979]  do_serror+0x68/0x130
[    3.010980]  el1_error+0x7c/0xdc
[    3.010982]  _raw_spin_unlock_irqrestore+0xc/0x48
[    3.010984]  clk_core_disable_lock+0x28/0x38
[    3.010985]  clk_disable+0x1c/0x30
[    3.010987]  regmap_mmio_write+0x54/0x68
[    3.010989]  _regmap_bus_reg_write+0x14/0x20
[    3.010990]  _regmap_write+0x60/0xa8
[    3.010992]  regmap_write+0x48/0x70
[    3.010994]  fsl_asrc_probe+0x258/0x660
[    3.010995]  platform_drv_probe+0x50/0xb0

Why this issue only happen at kernel reboot, it is because the ipg
clock is enabled in default after system reset, after used once, the
ipg clock is disabled, then reboot system, the issue happen.

Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
---

diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8dx.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8dx.dtsi
index d5bb55534c90..23474ee194b7 100644
--- a/arch/arm64/boot/dts/freescale/fsl-imx8dx.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-imx8dx.dtsi
@@ -3058,7 +3058,7 @@
 		interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>,
 			<GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&clk IMX8QXP_AUD_ASRC_0_IPG>,
-			<&clk IMX8QXP_CLK_DUMMY>,
+			<&clk IMX8QXP_AUD_ASRC_0_IPG>,
 			<&clk IMX8QXP_AUD_ACM_AUD_PLL_CLK0_CLK>,
 			<&clk IMX8QXP_AUD_ACM_AUD_PLL_CLK1_CLK>,
 			<&clk IMX8QXP_ACM_AUD_CLK0_SEL>,
@@ -3098,7 +3098,7 @@
 		interrupts = <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>,
 			<GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&clk IMX8QXP_AUD_ASRC_1_IPG>,
-			<&clk IMX8QXP_CLK_DUMMY>,
+			<&clk IMX8QXP_AUD_ASRC_1_IPG>,
 			<&clk IMX8QXP_AUD_ACM_AUD_PLL_CLK0_CLK>,
 			<&clk IMX8QXP_AUD_ACM_AUD_PLL_CLK1_CLK>,
 			<&clk IMX8QXP_ACM_AUD_CLK0_SEL>,