From: Robert Chiras <robert.chiras@nxp.com>
Date: Tue, 5 Dec 2017 07:24:24 +0000 (+0200)
Subject: MLK-16986-1: phy: Fix Mixel PHY driver best_match
X-Git-Tag: rel_imx_4.19.35_1.1.0~1816
X-Git-Url: https://git.somdevices.com/?a=commitdiff_plain;h=315579e08fc9ac07e9d3b62a07f73b28d9f27b59;p=linux.git

MLK-16986-1: phy: Fix Mixel PHY driver best_match

When setting up the CM, CN and CO decimal values for DPHY PLL, these
values should only be rounded up when a "best_match" is requested. Some
DSI receivers requires the DSI clock to be exactly matched with the
pixel clock.

Signed-off-by: Robert Chiras <robert.chiras@nxp.com>
Reviewed-by: Laurentiu Palcu <laurentiu.palcu@nxp.com
---

diff --git a/drivers/phy/phy-mixel-mipi-dsi.c b/drivers/phy/phy-mixel-mipi-dsi.c
index cd7192da076b..0b004002f9c0 100644
--- a/drivers/phy/phy-mixel-mipi-dsi.c
+++ b/drivers/phy/phy-mixel-mipi-dsi.c
@@ -146,7 +146,8 @@ int mixel_phy_mipi_set_phy_speed(struct phy *phy,
 	if (numerator < 16 || numerator > 255)
 		return -EINVAL;
 
-	numerator = DIV_ROUND_UP(numerator, denominator) * denominator;
+	if (best_match)
+		numerator = DIV_ROUND_UP(numerator, denominator) * denominator;
 
 	priv->divider.cn = 1;
 	if (denominator > 8) {