From: Allen Yan Date: Fri, 13 Oct 2017 09:01:53 +0000 (+0200) Subject: serial: mvebu-uart: add TX interrupt trigger for pulse interrupts X-Git-Tag: rel_imx_4.19.35_1.1.0~11323^2~46 X-Git-Url: https://git.somdevices.com/?a=commitdiff_plain;h=30434b0713a5f4ecf00e9ffd3d47053882b1909a;p=linux.git serial: mvebu-uart: add TX interrupt trigger for pulse interrupts Pulse interrupts (extended UART only) needs a change of state to trigger the TX interrupt. In addition to enabling the TX_READY_INT_EN flag, produce a FIFO state change from 'empty' to 'not full'. For this, write only one data byte in TX start, making the TX FIFO not empty, and wait for the TX interrupt to continue the transfer. Signed-off-by: Allen Yan Signed-off-by: Miquel Raynal Reviewed-by: Gregory CLEMENT Signed-off-by: Greg Kroah-Hartman --- diff --git a/drivers/tty/serial/mvebu-uart.c b/drivers/tty/serial/mvebu-uart.c index 6bd0c40008bb..e52248ec2689 100644 --- a/drivers/tty/serial/mvebu-uart.c +++ b/drivers/tty/serial/mvebu-uart.c @@ -165,8 +165,16 @@ static void mvebu_uart_stop_tx(struct uart_port *port) static void mvebu_uart_start_tx(struct uart_port *port) { - unsigned int ctl = readl(port->membase + UART_INTR(port)); + unsigned int ctl; + struct circ_buf *xmit = &port->state->xmit; + if (IS_EXTENDED(port) && !uart_circ_empty(xmit)) { + writel(xmit->buf[xmit->tail], port->membase + UART_TSH(port)); + xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); + port->icount.tx++; + } + + ctl = readl(port->membase + UART_INTR(port)); ctl |= CTRL_TX_RDY_INT(port); writel(ctl, port->membase + UART_INTR(port)); }