From: Josep Orga <jorga@somdevices.com>
Date: Fri, 13 Aug 2021 09:57:56 +0000 (+0200)
Subject: arm64: dts: imx8mm-somdevices.dtsi: Configure WiFi/BT pins.
X-Git-Tag: rel_imx_5.10.35_2.0.0-somdevices.0~34
X-Git-Url: https://git.somdevices.com/?a=commitdiff_plain;h=1c39afb8c0ac477a17b8027450777f826939f4d7;p=linux.git

arm64: dts: imx8mm-somdevices.dtsi: Configure WiFi/BT pins.

Signed-off-by: Josep Orga <jorga@somdevices.com>
---

diff --git a/arch/arm64/boot/dts/freescale/imx8mm-somdevices.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-somdevices.dtsi
index 8703d6983b91..4ef4f33c6285 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm-somdevices.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm-somdevices.dtsi
@@ -35,7 +35,7 @@
 
 	modem_reset: modem-reset {
 		compatible = "gpio-reset";
-		reset-gpios = <&gpio2 6 GPIO_ACTIVE_LOW>;
+		reset-gpios = <&gpio2 7 GPIO_ACTIVE_LOW>;
 		reset-delay-us = <2000>;
 		reset-post-delay-ms = <40>;
 		#reset-cells = <0>;
@@ -73,7 +73,7 @@
 		simple-audio-card,bitclock-master = <&btcpu>;
 
 		btcpu: simple-audio-card,cpu {
-			sound-dai = <&sai2>;
+			sound-dai = <&sai1>;
 			dai-tdm-slot-num = <2>;
 			dai-tdm-slot-width = <16>;
 		};
@@ -87,7 +87,8 @@
 		compatible = "mmc-pwrseq-simple";
 		pinctrl-names = "default";
 		pinctrl-0 = <&pinctrl_usdhc1_gpio>;
-		reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;
+		reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>,
+			      <&gpio2 6 GPIO_ACTIVE_LOW>;
 	};
 
 };
@@ -644,35 +645,19 @@
 
 	pinctrl_sai1: sai1grp {
 		fsl,pins = <
-			MX8MM_IOMUXC_SAI1_MCLK_SAI1_MCLK	0xd6
-			MX8MM_IOMUXC_SAI1_TXFS_SAI1_TX_SYNC	0xd6
-			MX8MM_IOMUXC_SAI1_RXD7_SAI1_TX_SYNC	0xd6
 			MX8MM_IOMUXC_SAI1_TXC_SAI1_TX_BCLK	0xd6
+			MX8MM_IOMUXC_SAI1_TXFS_SAI1_TX_SYNC	0xd6
 			MX8MM_IOMUXC_SAI1_TXD0_SAI1_TX_DATA0	0xd6
-			MX8MM_IOMUXC_SAI1_TXD1_SAI1_TX_DATA1	0xd6
-			MX8MM_IOMUXC_SAI1_TXD2_SAI1_TX_DATA2	0xd6
-			MX8MM_IOMUXC_SAI1_TXD3_SAI1_TX_DATA3	0xd6
-			MX8MM_IOMUXC_SAI1_TXD4_SAI1_TX_DATA4	0xd6
-			MX8MM_IOMUXC_SAI1_TXD5_SAI1_TX_DATA5	0xd6
-			MX8MM_IOMUXC_SAI1_TXD6_SAI1_TX_DATA6	0xd6
-			MX8MM_IOMUXC_SAI1_TXD7_SAI1_TX_DATA7	0xd6
+			MX8MM_IOMUXC_SAI1_RXD0_SAI1_RX_DATA0	0xd6
 		>;
 	};
 
 	pinctrl_sai1_dsd: sai1grp_dsd {
 		fsl,pins = <
-			MX8MM_IOMUXC_SAI1_MCLK_SAI1_MCLK	0xd6
-			MX8MM_IOMUXC_SAI1_TXFS_SAI1_TX_SYNC	0xd6
-			MX8MM_IOMUXC_SAI1_RXD7_SAI1_TX_DATA4	0xd6
 			MX8MM_IOMUXC_SAI1_TXC_SAI1_TX_BCLK	0xd6
+			MX8MM_IOMUXC_SAI1_TXFS_SAI1_TX_SYNC	0xd6
 			MX8MM_IOMUXC_SAI1_TXD0_SAI1_TX_DATA0	0xd6
-			MX8MM_IOMUXC_SAI1_TXD1_SAI1_TX_DATA1	0xd6
-			MX8MM_IOMUXC_SAI1_TXD2_SAI1_TX_DATA2	0xd6
-			MX8MM_IOMUXC_SAI1_TXD3_SAI1_TX_DATA3	0xd6
-			MX8MM_IOMUXC_SAI1_TXD4_SAI1_TX_DATA4	0xd6
-			MX8MM_IOMUXC_SAI1_TXD5_SAI1_TX_DATA5	0xd6
-			MX8MM_IOMUXC_SAI1_TXD6_SAI1_TX_DATA6	0xd6
-			MX8MM_IOMUXC_SAI1_TXD7_SAI1_TX_DATA7	0xd6
+			MX8MM_IOMUXC_SAI1_RXD0_SAI1_RX_DATA0	0xd6
 		>;
 	};
 
@@ -690,11 +675,11 @@
 
 	pinctrl_uart1: uart1grp {
 		fsl,pins = <
-			MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX     0x140
-			MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX     0x140
-			MX8MM_IOMUXC_UART3_RXD_UART1_DCE_CTS_B  0x140
-			MX8MM_IOMUXC_UART3_TXD_UART1_DCE_RTS_B  0x140
-			MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6        0x19
+			MX8MM_IOMUXC_SAI2_TXFS_UART1_DCE_CTS_B	0x140
+			MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX	0x140
+			MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX	0x140
+			MX8MM_IOMUXC_SAI2_RXD0_UART1_DCE_RTS_B	0x140
+			MX8MM_IOMUXC_SD1_DATA5_GPIO2_IO7	0x19
 		>;
 	};
 
@@ -717,6 +702,7 @@
 	pinctrl_usdhc1_gpio: usdhc1grpgpio {
 		fsl,pins = <
 			MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10	0x41
+			MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6	0x19
 		>;
 	};