From: Ye Li Date: Fri, 4 Jun 2021 06:49:48 +0000 (-0700) Subject: LFU-161 imx8m: Fix pad DSE issue for imx8mm/mn/mp X-Git-Tag: rel_imx_5.10.35_2.0.0-somdevices.0~58^2 X-Git-Url: https://git.somdevices.com/?a=commitdiff_plain;h=1c38adcc56d9aa711a92b47fdfd5e9e79fbbcd92;p=u-boot.git LFU-161 imx8m: Fix pad DSE issue for imx8mm/mn/mp According to RM, 8MM/MN/MP pad only have 4 valid DSE values. And DSE2 and DSE4 are different with current definitions in iomux-v3.h. Fix the issue to align with RM. Signed-off-by: Ye Li Acked-by: Peng Fan --- diff --git a/arch/arm/include/asm/mach-imx/iomux-v3.h b/arch/arm/include/asm/mach-imx/iomux-v3.h index 34b9f128a6..541c8ea842 100644 --- a/arch/arm/include/asm/mach-imx/iomux-v3.h +++ b/arch/arm/include/asm/mach-imx/iomux-v3.h @@ -87,15 +87,6 @@ typedef u64 iomux_v3_cfg_t; #define MUX_MODE_LPSR ((iomux_v3_cfg_t)IOMUX_CONFIG_LPSR << \ MUX_MODE_SHIFT) #ifdef CONFIG_IMX8M -#define PAD_CTL_DSE0 (0x0 << 0) -#define PAD_CTL_DSE1 (0x1 << 0) -#define PAD_CTL_DSE2 (0x2 << 0) -#define PAD_CTL_DSE3 (0x3 << 0) -#define PAD_CTL_DSE4 (0x4 << 0) -#define PAD_CTL_DSE5 (0x5 << 0) -#define PAD_CTL_DSE6 (0x6 << 0) -#define PAD_CTL_DSE7 (0x7 << 0) - #define PAD_CTL_FSEL0 (0x0 << 3) #define PAD_CTL_FSEL1 (0x1 << 3) #define PAD_CTL_FSEL2 (0x2 << 3) @@ -105,8 +96,20 @@ typedef u64 iomux_v3_cfg_t; #define PAD_CTL_PUE (0x1 << 6) #define PAD_CTL_HYS (0x1 << 7) #if defined(CONFIG_IMX8MM) || defined(CONFIG_IMX8MN) || defined(CONFIG_IMX8MP) +#define PAD_CTL_DSE1 (0x0 << 1) +#define PAD_CTL_DSE2 (0x2 << 1) +#define PAD_CTL_DSE4 (0x1 << 1) +#define PAD_CTL_DSE6 (0x3 << 1) #define PAD_CTL_PE (0x1 << 8) #else +#define PAD_CTL_DSE0 (0x0 << 0) +#define PAD_CTL_DSE1 (0x1 << 0) +#define PAD_CTL_DSE2 (0x2 << 0) +#define PAD_CTL_DSE3 (0x3 << 0) +#define PAD_CTL_DSE4 (0x4 << 0) +#define PAD_CTL_DSE5 (0x5 << 0) +#define PAD_CTL_DSE6 (0x6 << 0) +#define PAD_CTL_DSE7 (0x7 << 0) #define PAD_CTL_LVTTL (0x1 << 8) #endif