From: Xiang Chen Date: Fri, 17 Apr 2020 06:07:57 +0000 (+0800) Subject: mtd: spi-nor: Enable locking for n25q128a11 X-Git-Tag: rel_imx_5.10.35_2.0.0-somdevices.0~1957^2~4^2~21 X-Git-Url: https://git.somdevices.com/?a=commitdiff_plain;h=150ccc181588b018891dc973f47905d574677b21;p=linux.git mtd: spi-nor: Enable locking for n25q128a11 As 4bit block protection patchset for some micron models are merged, n25q128a11 also uses 4 bit Block Protection scheme, so enable locking for it. Tested it on n25q128a11, the locking functions work well. Signed-off-by: Xiang Chen Reviewed-by: Jungseung Lee Tested-by: Shreyas Joshi Signed-off-by: Tudor Ambarus --- diff --git a/drivers/mtd/spi-nor/micron-st.c b/drivers/mtd/spi-nor/micron-st.c index 6c034b9718e2..02c0b53f6097 100644 --- a/drivers/mtd/spi-nor/micron-st.c +++ b/drivers/mtd/spi-nor/micron-st.c @@ -29,7 +29,9 @@ static const struct flash_info st_parts[] = { { "n25q064a", INFO(0x20bb17, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_QUAD_READ) }, { "n25q128a11", INFO(0x20bb18, 0, 64 * 1024, 256, - SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) }, + SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | + SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | + SPI_NOR_4BIT_BP | SPI_NOR_BP3_SR_BIT6) }, { "n25q128a13", INFO(0x20ba18, 0, 64 * 1024, 256, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) }, { "mt25ql256a", INFO6(0x20ba19, 0x104400, 64 * 1024, 512,