From: Josep Orga <jorga@somdevices.com>
Date: Wed, 27 Nov 2019 10:40:34 +0000 (+0100)
Subject: imx6ull-somdevices.dts: Add support to single/dual ethernet.
X-Git-Tag: C0P2-H0.0--20200415~19
X-Git-Url: https://git.somdevices.com/?a=commitdiff_plain;h=134fa1a5c234833690645190ddc3a996d75d11f5;p=linux.git

imx6ull-somdevices.dts: Add support to single/dual ethernet.

Signed-off-by: Josep Orga <jorga@somdevices.com>
---

diff --git a/arch/arm/boot/dts/imx6ull-somdevices.dts b/arch/arm/boot/dts/imx6ull-somdevices.dts
index 754c7c140d16..8f500e8a008f 100644
--- a/arch/arm/boot/dts/imx6ull-somdevices.dts
+++ b/arch/arm/boot/dts/imx6ull-somdevices.dts
@@ -5,9 +5,11 @@
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
  */
-
+/* #define DUAL_ETH */
 /dts-v1/;
 
+#define DUAL_ETH
+
 #include <dt-bindings/input/input.h>
 #include "imx6ull.dtsi"
 
@@ -169,34 +171,61 @@
 
 &fec1 {
 	pinctrl-names = "default";
+#ifdef DUAL_ETH
 	pinctrl-0 = <&pinctrl_enet1>;
+#else
+	pinctrl-0 = <&pinctrl_enet1 &pinctrl_enet1_mdio>;
+#endif
 	phy-mode = "rmii";
 	phy-handle = <&ethphy0>;
+	phy-reset-gpios = <&gpio5 10 GPIO_ACTIVE_LOW>;
+	phy-reset-duration = <26>;
+	phy-reset-in-suspend;
 	status = "okay";
+
+#ifndef DUAL_ETH
+	mdio {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		ethphy0: ethernet-phy@0 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			smsc,disable-energy-detect;
+			reg = <0>;
+		};
+	};
+#endif
 };
 
+#ifdef DUAL_ETH
 &fec2 {
 	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_enet2>;
+	pinctrl-0 = <&pinctrl_enet2 &pinctrl_enet2_mdio>;
 	phy-mode = "rmii";
 	phy-handle = <&ethphy1>;
+	phy-reset-gpios = <&gpio5 11 GPIO_ACTIVE_LOW>;
+	phy-reset-duration = <26>;
+	phy-reset-in-suspend;
 	status = "okay";
 
 	mdio {
 		#address-cells = <1>;
 		#size-cells = <0>;
 
-		ethphy0: ethernet-phy@2 {
+		ethphy0: ethernet-phy@0 {
 			compatible = "ethernet-phy-ieee802.3-c22";
-			reg = <2>;
+			smsc,disable-energy-detect;
+			reg = <0>;
 		};
 
 		ethphy1: ethernet-phy@1 {
 			compatible = "ethernet-phy-ieee802.3-c22";
+			smsc,disable-energy-detect;
 			reg = <1>;
 		};
 	};
 };
+#endif
 
 &flexcan1 {
 	pinctrl-names = "default";
@@ -306,6 +335,7 @@
 
 	pinctrl_enet1: enet1grp {
 		fsl,pins = <
+			MX6ULL_PAD_BOOT_MODE0__GPIO5_IO10	0x0b0b0//0x70a1
 			MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN	0x1b0b0
 			MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER	0x1b0b0
 			MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00	0x1b0b0
@@ -319,8 +349,7 @@
 
 	pinctrl_enet2: enet2grp {
 		fsl,pins = <
-			MX6UL_PAD_GPIO1_IO07__ENET2_MDC		0x1b0b0
-			MX6UL_PAD_GPIO1_IO06__ENET2_MDIO	0x1b0b0
+			MX6ULL_PAD_BOOT_MODE1__GPIO5_IO11	0x0b0b0//0x70a1
 			MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN	0x1b0b0
 			MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER	0x1b0b0
 			MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00	0x1b0b0
@@ -332,6 +361,20 @@
 		>;
 	};
 
+	pinctrl_enet1_mdio: mdioenet1grp {
+		fsl,pins = <
+			MX6UL_PAD_GPIO1_IO07__ENET1_MDC		0x1b0b0
+			MX6UL_PAD_GPIO1_IO06__ENET1_MDIO	0x1b0b0
+		>;
+	};
+
+	pinctrl_enet2_mdio: mdioenet2grp {
+		fsl,pins = <
+			MX6UL_PAD_GPIO1_IO07__ENET2_MDC		0x1b0b0
+			MX6UL_PAD_GPIO1_IO06__ENET2_MDIO	0x1b0b0
+		>;
+	};
+
 	pinctrl_flexcan1: flexcan1grp{
 		fsl,pins = <
 			MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX	0x1b020