From: Fugang Duan Date: Fri, 6 Feb 2015 08:42:46 +0000 (+0800) Subject: MLK-10463-1 ARM: imx: init ENET RGMII tx clock source X-Git-Tag: C0P2-H0.0--20200415~4765 X-Git-Url: https://git.somdevices.com/?a=commitdiff_plain;h=1140ceaad07da100b9fd4e739027552bd732bc1c;p=linux.git MLK-10463-1 ARM: imx: init ENET RGMII tx clock source Init ENET RGMII tx clock source, set GPR5[9] to select clock from internal PLL_enet. And set phy VDDIO to 1.8V that get better signal quality. Signed-off-by: Fugang Duan (cherry picked from commit: d7a171fcf5218166f558428610ca8e9cb9f7e830) --- diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c index cbdee5106bf4..2a549698faa2 100644 --- a/arch/arm/mach-imx/mach-imx6q.c +++ b/arch/arm/mach-imx/mach-imx6q.c @@ -113,6 +113,10 @@ static int ar8031_phy_fixup(struct phy_device *dev) { u16 val; + /* Set RGMII IO voltage to 1.8V */ + phy_write(dev, 0x1d, 0x1f); + phy_write(dev, 0x1e, 0x8); + /* disable phy AR8031 SmartEEE function. */ phy_write(dev, 0xd, 0x3); phy_write(dev, 0xe, 0x805d); @@ -258,6 +262,18 @@ static void __init imx6q_axi_init(void) } } +static void __init imx6q_enet_clk_sel(void) +{ + struct regmap *gpr; + + gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr"); + if (!IS_ERR(gpr)) + regmap_update_bits(gpr, IOMUXC_GPR5, + IMX6Q_GPR5_ENET_TX_CLK_SEL, IMX6Q_GPR5_ENET_TX_CLK_SEL); + else + pr_err("failed to find fsl,imx6q-iomux-gpr regmap\n"); +} + #define OCOTP_MACn(n) (0x00000620 + (n) * 0x10) void __init imx6_enet_mac_init(const char *enet_compat, const char *ocotp_compat) { @@ -341,6 +357,8 @@ static inline void imx6q_enet_init(void) imx6_enet_mac_init("fsl,imx6q-fec", "fsl,imx6q-ocotp"); imx6q_enet_phy_init(); imx6q_1588_init(); + if (cpu_is_imx6q() && imx_get_soc_revision() == IMX_CHIP_REVISION_2_0) + imx6q_enet_clk_sel(); } static void __init imx6q_init_machine(void) diff --git a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h index c8e0164c5423..57be5496a08c 100644 --- a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h +++ b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h @@ -243,6 +243,7 @@ #define IMX6Q_GPR4_IPU_RD_CACHE_CTL BIT(0) #define IMX6Q_GPR5_L2_CLK_STOP BIT(8) +#define IMX6Q_GPR5_ENET_TX_CLK_SEL BIT(9) #define IMX6Q_GPR6_IPU1_ID00_WR_QOS_MASK (0xf << 0) #define IMX6Q_GPR6_IPU1_ID01_WR_QOS_MASK (0xf << 4)