From: Haibo Chen <haibo.chen@nxp.com>
Date: Wed, 14 Mar 2018 09:15:23 +0000 (+0800)
Subject: MLK-17586-3 i.MX7ULP: change USDHC clock rate
X-Git-Tag: rel_imx_4.9.88_2.0.0_ga~26
X-Git-Url: https://git.somdevices.com/?a=commitdiff_plain;h=07ef0fab23204684d82f27baf721a72b247f30c5;p=u-boot.git

MLK-17586-3 i.MX7ULP: change USDHC clock rate

Change USDHC0 and USDHC1 per clock source from APLL_PFD1,
and set the APll_PFD1 clock rate to 352.8MHz.

Also gate off APll_PFD1/2/3 before boot OS, otherwise set
the clock rate of APll_PFD1/2/3 during OS boot up will triger
some warning message.

Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
---

diff --git a/arch/arm/cpu/armv7/mx7ulp/clock.c b/arch/arm/cpu/armv7/mx7ulp/clock.c
index 98d40d6c1d..eb858fa8ac 100644
--- a/arch/arm/cpu/armv7/mx7ulp/clock.c
+++ b/arch/arm/cpu/armv7/mx7ulp/clock.c
@@ -150,8 +150,8 @@ void init_clk_usdhc(u32 index)
 		/*Disable the clock before configure it */
 		pcc_clock_enable(PER_CLK_USDHC0, false);
 
-		/* 158MHz / 1 = 158MHz */
-		pcc_clock_sel(PER_CLK_USDHC0, SCG_NIC1_CLK);
+		/* 352.8MHz / 1 = 352.8MHz */
+		pcc_clock_sel(PER_CLK_USDHC0, SCG_APLL_PFD1_CLK);
 		pcc_clock_div_config(PER_CLK_USDHC0, false, 1);
 		pcc_clock_enable(PER_CLK_USDHC0, true);
 		break;
@@ -159,9 +159,9 @@ void init_clk_usdhc(u32 index)
 		/*Disable the clock before configure it */
 		pcc_clock_enable(PER_CLK_USDHC1, false);
 
-		/* 158MHz / 1 = 158MHz */
-		pcc_clock_sel(PER_CLK_USDHC1, SCG_NIC1_CLK);
-		pcc_clock_div_config(PER_CLK_USDHC1, false, 1);
+		/* 352.8MHz / 2 = 176.4MHz */
+		pcc_clock_sel(PER_CLK_USDHC1, SCG_APLL_PFD1_CLK);
+		pcc_clock_div_config(PER_CLK_USDHC1, false, 2);
 		pcc_clock_enable(PER_CLK_USDHC1, true);
 		break;
 	default:
@@ -304,8 +304,8 @@ void clock_init(void)
 
 	scg_a7_init_core_clk();
 
-	/* APLL PFD1 = 270Mhz, PFD2=345.6Mhz, PFD3=800Mhz */
-	scg_enable_pll_pfd(SCG_APLL_PFD1_CLK, 35);
+	/* APLL PFD1 = 352.8Mhz, PFD2=340.2Mhz, PFD3=793.8Mhz */
+	scg_enable_pll_pfd(SCG_APLL_PFD1_CLK, 27);
 	scg_enable_pll_pfd(SCG_APLL_PFD2_CLK, 28);
 	scg_enable_pll_pfd(SCG_APLL_PFD3_CLK, 12);
 
diff --git a/arch/arm/cpu/armv7/mx7ulp/scg.c b/arch/arm/cpu/armv7/mx7ulp/scg.c
index bb8326dbd1..992cb4e93d 100644
--- a/arch/arm/cpu/armv7/mx7ulp/scg.c
+++ b/arch/arm/cpu/armv7/mx7ulp/scg.c
@@ -714,6 +714,61 @@ int scg_enable_pll_pfd(enum scg_clk clk, u32 frac)
 	return 0;
 }
 
+int scg_disable_pll_pfd(enum scg_clk clk)
+{
+	u32 reg;
+	u32 gate;
+	u32 addr;
+
+	switch (clk) {
+	case SCG_SPLL_PFD0_CLK:
+	case SCG_APLL_PFD0_CLK:
+		gate = SCG_PLL_PFD0_GATE_MASK;
+
+		if (clk == SCG_SPLL_PFD0_CLK)
+			addr = (u32)(&scg1_regs->spllpfd);
+		else
+			addr = (u32)(&scg1_regs->apllpfd);
+		break;
+	case SCG_SPLL_PFD1_CLK:
+	case SCG_APLL_PFD1_CLK:
+		gate = SCG_PLL_PFD1_GATE_MASK;
+
+		if (clk == SCG_SPLL_PFD1_CLK)
+			addr = (u32)(&scg1_regs->spllpfd);
+		else
+			addr = (u32)(&scg1_regs->apllpfd);
+		break;
+	case SCG_SPLL_PFD2_CLK:
+	case SCG_APLL_PFD2_CLK:
+		gate = SCG_PLL_PFD2_GATE_MASK;
+
+		if (clk == SCG_SPLL_PFD2_CLK)
+			addr = (u32)(&scg1_regs->spllpfd);
+		else
+			addr = (u32)(&scg1_regs->apllpfd);
+		break;
+	case SCG_SPLL_PFD3_CLK:
+	case SCG_APLL_PFD3_CLK:
+		gate = SCG_PLL_PFD3_GATE_MASK;
+
+		if (clk == SCG_SPLL_PFD3_CLK)
+			addr = (u32)(&scg1_regs->spllpfd);
+		else
+			addr = (u32)(&scg1_regs->apllpfd);
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	/* Gate the PFD */
+	reg = readl(addr);
+	reg |= gate;
+	writel(reg, addr);
+
+	return 0;
+}
+
 #define SIM_MISC_CTRL0_USB_PLL_EN_MASK (0x1 << 2)
 int scg_enable_usb_pll(bool usb_control)
 {
diff --git a/arch/arm/cpu/armv7/mx7ulp/soc.c b/arch/arm/cpu/armv7/mx7ulp/soc.c
index 715a8eeb4a..c5599b72a9 100644
--- a/arch/arm/cpu/armv7/mx7ulp/soc.c
+++ b/arch/arm/cpu/armv7/mx7ulp/soc.c
@@ -288,6 +288,9 @@ void arch_preboot_os(void)
 #if defined(CONFIG_VIDEO_MXS)
 	lcdif_power_down();
 #endif
+	scg_disable_pll_pfd(SCG_APLL_PFD1_CLK);
+	scg_disable_pll_pfd(SCG_APLL_PFD2_CLK);
+	scg_disable_pll_pfd(SCG_APLL_PFD3_CLK);
 }
 
 #ifdef CONFIG_ENV_IS_IN_MMC
diff --git a/arch/arm/include/asm/arch-mx7ulp/scg.h b/arch/arm/include/asm/arch-mx7ulp/scg.h
index f46e52baba..bf1005dd4e 100644
--- a/arch/arm/include/asm/arch-mx7ulp/scg.h
+++ b/arch/arm/include/asm/arch-mx7ulp/scg.h
@@ -326,6 +326,7 @@ typedef struct scg_regs {
 
 u32 scg_clk_get_rate(enum scg_clk clk);
 int scg_enable_pll_pfd(enum scg_clk clk, u32 frac);
+int scg_disable_pll_pfd(enum scg_clk clk);
 int scg_enable_usb_pll(bool usb_control);
 u32 decode_pll(enum pll_clocks pll);