MLK-11420 ARM: dts: imx7d-12x12-lpddr3-arm2: add sai<->WM8958 sound card support

add sai<->WM8958 sound card support

Signed-off-by: Zidan Wang <zidan.wang@freescale.com>

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 41a4fde..c6a2b74 100644 (file)
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -442,7 +442,8 @@ dtb-$(CONFIG_SOC_IMX7D) += \
        imx7d-12x12-lpddr3-arm2-m4.dtb \
        imx7d-12x12-lpddr3-arm2-ecspi.dtb \
        imx7d-12x12-lpddr3-arm2-enet2.dtb \
-       imx7d-12x12-lpddr3-arm2-mipi_dsi.dtb
+       imx7d-12x12-lpddr3-arm2-mipi_dsi.dtb \
+       imx7d-12x12-lpddr3-arm2-sai.dtb
 dtb-$(CONFIG_SOC_LS1021A) += \
        ls1021a-qds.dtb \
        ls1021a-twr.dtb

diff --git a/arch/arm/boot/dts/imx7d-12x12-lpddr3-arm2-sai.dts b/arch/arm/boot/dts/imx7d-12x12-lpddr3-arm2-sai.dts
new file mode 100644 (file)
index 0000000..c2c0da5
--- /dev/null
+++ b/arch/arm/boot/dts/imx7d-12x12-lpddr3-arm2-sai.dts
@@ -0,0 +1,43 @@
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "imx7d-12x12-lpddr3-arm2.dts"
+
+/ {
+       sound {
+               compatible = "fsl,imx7d-12x12-lpddr3-arm2-wm8958",
+                           "fsl,imx-audio-wm8958";
+               model = "wm8958-audio";
+               cpu-dai = <&sai1>;
+               audio-codec = <&codec>;
+               codec-master;
+               hp-det-gpios = <&gpio1 12 1>;
+       };
+};
+
+&iomuxc {
+       pinctrl-0 = <&pinctrl_hog_1>;
+};
+
+&sai1 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_sai1>;
+       status = "okay";
+};
+
+&sdma {
+       status = "okay";
+};
+
+&sim1 {
+       status = "disabled";
+};
+
+&usdhc2 {
+       no-1-8-v;
+};

diff --git a/arch/arm/boot/dts/imx7d-12x12-lpddr3-arm2.dts b/arch/arm/boot/dts/imx7d-12x12-lpddr3-arm2.dts
index 7cc278e..122e9a1 100644 (file)
--- a/arch/arm/boot/dts/imx7d-12x12-lpddr3-arm2.dts
+++ b/arch/arm/boot/dts/imx7d-12x12-lpddr3-arm2.dts
@@ -32,6 +32,24 @@
                #address-cells = <1>;
                #size-cells = <0>;
 
+               reg_aud_1v8: aud_1v8 {
+                       compatible = "regulator-fixed";
+                       regulator-name = "AUD_1V8";
+                       regulator-min-microvolt = <1800000>;
+                       regulator-max-microvolt = <1800000>;
+                       gpio = <&gpio1 13 GPIO_ACTIVE_HIGH>;
+                       enable-active-high;
+               };
+
+               reg_coedc_5v: coedc_5v {
+                       compatible = "regulator-fixed";
+                       regulator-name = "CODEC_5V";
+                       regulator-min-microvolt = <5000000>;
+                       regulator-max-microvolt = <5000000>;
+                       gpio = <&gpio1 13 GPIO_ACTIVE_HIGH>;
+                       enable-active-high;
+               };
+
                reg_sd1_vmmc: sd1_vmmc{
                        compatible = "regulator-fixed";
                        regulator-name = "VCC_SD1";
@@ -259,11 +277,29 @@
                gpio-controller;
                #gpio-cells = <2>;
        };
+
+       codec: wm8958@1a {
+               compatible = "wlf,wm8958";
+               reg = <0x1a>;
+               clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>,
+                        <&clks IMX7D_CLK_DUMMY>;
+               clock-names = "mclk1", "mclk2";
+
+               DBVDD1-supply = <&reg_aud_1v8>;
+               DBVDD2-supply = <&reg_aud_1v8>;
+               DBVDD3-supply = <&reg_aud_1v8>;
+               AVDD2-supply = <&reg_aud_1v8>;
+               CPVDD-supply = <&reg_aud_1v8>;
+               SPKVDD1-supply = <&reg_coedc_5v>;
+               SPKVDD2-supply = <&reg_coedc_5v>;
+               wlf,ldo1ena;
+               wlf,ldo2ena;
+       };
 };
 
 &iomuxc {
        pinctrl-names = "default";
-       pinctrl-0 = <&pinctrl_hog_1>;
+       pinctrl-0 = <&pinctrl_hog_1 &pinctrl_hog_sd2_vselect>;
 
        imx7d-12x12-lpddr3-arm2 {
 
@@ -332,13 +368,18 @@
                                MX7D_PAD_SD2_CD_B__GPIO5_IO9      0x17059
                                MX7D_PAD_SD2_WP__GPIO5_IO10       0x17059
                                MX7D_PAD_SD2_RESET_B__GPIO5_IO11  0x17059
-                               MX7D_PAD_GPIO1_IO12__SD2_VSELECT  0x17059
 
                                 MX7D_PAD_ECSPI1_SCLK__GPIO4_IO16  0x59
                                 MX7D_PAD_ECSPI1_MOSI__GPIO4_IO17  0x59
                        >;
                };
 
+               pinctrl_hog_sd2_vselect: hoggrp_sd2vselect {
+                       fsl,pins = <
+                               MX7D_PAD_GPIO1_IO12__SD2_VSELECT  0x59
+                       >;
+               };
+
                pinctrl_i2c1_1: i2c1grp-1 {
                        fsl,pins = <
                                MX7D_PAD_I2C1_SDA__I2C1_SDA          0x4000007f
@@ -411,6 +452,29 @@
                        >;
                };
 
+               pinctrl_sai1: sai1grp {
+                       fsl,pins = <
+                               MX7D_PAD_SAI1_MCLK__SAI1_MCLK           0x1f
+                               MX7D_PAD_SAI1_TX_BCLK__SAI1_TX_BCLK     0x1f
+                               MX7D_PAD_SAI1_TX_SYNC__SAI1_TX_SYNC     0x1f
+                               MX7D_PAD_SAI1_RX_SYNC__SAI1_RX_SYNC     0x1f
+                               MX7D_PAD_SAI1_RX_DATA__SAI1_RX_DATA0    0x1f
+                               MX7D_PAD_SAI1_TX_DATA__SAI1_TX_DATA0    0
+
+                               MX7D_PAD_GPIO1_IO12__GPIO1_IO12         0x59
+                               MX7D_PAD_GPIO1_IO13__GPIO1_IO13         0x59
+                       >;
+               };
+
+               pinctrl_sai2: sai2grp {
+                       fsl,pins = <
+                               MX7D_PAD_SAI2_TX_BCLK__SAI2_TX_BCLK     0x1f
+                               MX7D_PAD_SAI2_TX_SYNC__SAI2_TX_SYNC     0x1f
+                               MX7D_PAD_SAI2_RX_DATA__SAI2_RX_DATA0    0x1f
+                               MX7D_PAD_SAI2_TX_DATA__SAI2_TX_DATA0    0
+                       >;
+               };
+
                pinctrl_uart1_1: uart1grp-1 {
                        fsl,pins = <
                                MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX 0x79