size = SZ_128K;
break;
case 1:
- core_rsrc = SC_R_HIFI;
+ core_rsrc = SC_R_DSP;
aux_core_ram = 0x596f8000;
size = SZ_2K;
break;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
- RPC_SVC(&msg) = SC_RPC_SVC_IRQ;
- RPC_FUNC(&msg) = IRQ_FUNC_ENABLE;
+ RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_IRQ;
+ RPC_FUNC(&msg) = (uint8_t) IRQ_FUNC_ENABLE;
RPC_U32(&msg, 0) = mask;
RPC_U16(&msg, 4) = resource;
RPC_U8(&msg, 6) = group;
- RPC_U8(&msg, 7) = enable;
+ RPC_U8(&msg, 7) = (uint8_t) enable;
RPC_SIZE(&msg) = 3;
sc_call_rpc(ipc, &msg, false);
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
- RPC_SVC(&msg) = SC_RPC_SVC_IRQ;
- RPC_FUNC(&msg) = IRQ_FUNC_STATUS;
+ RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_IRQ;
+ RPC_FUNC(&msg) = (uint8_t) IRQ_FUNC_STATUS;
RPC_U16(&msg, 0) = resource;
RPC_U8(&msg, 2) = group;
RPC_SIZE(&msg) = 2;
sc_call_rpc(ipc, &msg, false);
if (status != NULL)
+ {
*status = RPC_U32(&msg, 0);
+ }
+
result = RPC_R8(&msg);
return (sc_err_t) result;
}
MISC_FUNC_DEBUG_OUT = 10, /*!< Index for misc_debug_out() RPC call */
MISC_FUNC_WAVEFORM_CAPTURE = 6, /*!< Index for misc_waveform_capture() RPC call */
MISC_FUNC_BUILD_INFO = 15, /*!< Index for misc_build_info() RPC call */
+ MISC_FUNC_UNIQUE_ID = 19, /*!< Index for misc_unique_id() RPC call */
MISC_FUNC_SET_ARI = 3, /*!< Index for misc_set_ari() RPC call */
MISC_FUNC_BOOT_STATUS = 7, /*!< Index for misc_boot_status() RPC call */
MISC_FUNC_BOOT_DONE = 14, /*!< Index for misc_boot_done() RPC call */
MISC_FUNC_OTP_FUSE_READ = 11, /*!< Index for misc_otp_fuse_read() RPC call */
+ MISC_FUNC_OTP_FUSE_WRITE = 17, /*!< Index for misc_otp_fuse_write() RPC call */
MISC_FUNC_SET_TEMP = 12, /*!< Index for misc_set_temp() RPC call */
MISC_FUNC_GET_TEMP = 13, /*!< Index for misc_get_temp() RPC call */
MISC_FUNC_GET_BOOT_DEV = 16, /*!< Index for misc_get_boot_dev() RPC call */
+ MISC_FUNC_GET_BUTTON_STATUS = 18, /*!< Index for misc_get_button_status() RPC call */
} misc_func_t;
/* Functions */
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
- RPC_SVC(&msg) = SC_RPC_SVC_MISC;
- RPC_FUNC(&msg) = MISC_FUNC_SET_CONTROL;
+ RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_MISC;
+ RPC_FUNC(&msg) = (uint8_t) MISC_FUNC_SET_CONTROL;
RPC_U32(&msg, 0) = ctrl;
RPC_U32(&msg, 4) = val;
RPC_U16(&msg, 8) = resource;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
- RPC_SVC(&msg) = SC_RPC_SVC_MISC;
- RPC_FUNC(&msg) = MISC_FUNC_GET_CONTROL;
+ RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_MISC;
+ RPC_FUNC(&msg) = (uint8_t) MISC_FUNC_GET_CONTROL;
RPC_U32(&msg, 0) = ctrl;
RPC_U16(&msg, 4) = resource;
RPC_SIZE(&msg) = 3;
sc_call_rpc(ipc, &msg, false);
if (val != NULL)
+ {
*val = RPC_U32(&msg, 0);
+ }
+
result = RPC_R8(&msg);
return (sc_err_t) result;
}
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
- RPC_SVC(&msg) = SC_RPC_SVC_MISC;
- RPC_FUNC(&msg) = MISC_FUNC_SET_MAX_DMA_GROUP;
+ RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_MISC;
+ RPC_FUNC(&msg) = (uint8_t) MISC_FUNC_SET_MAX_DMA_GROUP;
RPC_U8(&msg, 0) = pt;
RPC_U8(&msg, 1) = max;
RPC_SIZE(&msg) = 2;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
- RPC_SVC(&msg) = SC_RPC_SVC_MISC;
- RPC_FUNC(&msg) = MISC_FUNC_SET_DMA_GROUP;
+ RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_MISC;
+ RPC_FUNC(&msg) = (uint8_t) MISC_FUNC_SET_DMA_GROUP;
RPC_U16(&msg, 0) = resource;
RPC_U8(&msg, 2) = group;
RPC_SIZE(&msg) = 2;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
- RPC_SVC(&msg) = SC_RPC_SVC_MISC;
- RPC_FUNC(&msg) = MISC_FUNC_SECO_IMAGE_LOAD;
+ RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_MISC;
+ RPC_FUNC(&msg) = (uint8_t) MISC_FUNC_SECO_IMAGE_LOAD;
RPC_U32(&msg, 0) = addr_src;
RPC_U32(&msg, 4) = addr_dst;
RPC_U32(&msg, 8) = len;
- RPC_U8(&msg, 12) = fw;
+ RPC_U8(&msg, 12) = (uint8_t) fw;
RPC_SIZE(&msg) = 5;
sc_call_rpc(ipc, &msg, false);
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
- RPC_SVC(&msg) = SC_RPC_SVC_MISC;
- RPC_FUNC(&msg) = MISC_FUNC_SECO_AUTHENTICATE;
+ RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_MISC;
+ RPC_FUNC(&msg) = (uint8_t) MISC_FUNC_SECO_AUTHENTICATE;
RPC_U32(&msg, 0) = addr_meta;
RPC_U8(&msg, 4) = cmd;
RPC_SIZE(&msg) = 3;
sc_rpc_msg_t msg;
RPC_VER(&msg) = SC_RPC_VERSION;
- RPC_SVC(&msg) = SC_RPC_SVC_MISC;
- RPC_FUNC(&msg) = MISC_FUNC_DEBUG_OUT;
+ RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_MISC;
+ RPC_FUNC(&msg) = (uint8_t) MISC_FUNC_DEBUG_OUT;
RPC_U8(&msg, 0) = ch;
RPC_SIZE(&msg) = 2;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
- RPC_SVC(&msg) = SC_RPC_SVC_MISC;
- RPC_FUNC(&msg) = MISC_FUNC_WAVEFORM_CAPTURE;
- RPC_U8(&msg, 0) = enable;
+ RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_MISC;
+ RPC_FUNC(&msg) = (uint8_t) MISC_FUNC_WAVEFORM_CAPTURE;
+ RPC_U8(&msg, 0) = (uint8_t) enable;
RPC_SIZE(&msg) = 2;
sc_call_rpc(ipc, &msg, false);
sc_rpc_msg_t msg;
RPC_VER(&msg) = SC_RPC_VERSION;
- RPC_SVC(&msg) = SC_RPC_SVC_MISC;
- RPC_FUNC(&msg) = MISC_FUNC_BUILD_INFO;
+ RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_MISC;
+ RPC_FUNC(&msg) = (uint8_t) MISC_FUNC_BUILD_INFO;
RPC_SIZE(&msg) = 1;
sc_call_rpc(ipc, &msg, false);
if (build != NULL)
+ {
*build = RPC_U32(&msg, 0);
+ }
+
if (commit != NULL)
+ {
*commit = RPC_U32(&msg, 4);
+ }
+
+ return;
+}
+
+void sc_misc_unique_id(sc_ipc_t ipc, uint32_t *id_l,
+ uint32_t *id_h)
+{
+ sc_rpc_msg_t msg;
+
+ RPC_VER(&msg) = SC_RPC_VERSION;
+ RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_MISC;
+ RPC_FUNC(&msg) = (uint8_t) MISC_FUNC_UNIQUE_ID;
+ RPC_SIZE(&msg) = 1;
+
+ sc_call_rpc(ipc, &msg, false);
+
+ if (id_l != NULL)
+ {
+ *id_l = RPC_U32(&msg, 0);
+ }
+
+ if (id_h != NULL)
+ {
+ *id_h = RPC_U32(&msg, 4);
+ }
+
return;
}
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
- RPC_SVC(&msg) = SC_RPC_SVC_MISC;
- RPC_FUNC(&msg) = MISC_FUNC_SET_ARI;
+ RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_MISC;
+ RPC_FUNC(&msg) = (uint8_t) MISC_FUNC_SET_ARI;
RPC_U16(&msg, 0) = resource;
RPC_U16(&msg, 2) = resource_mst;
RPC_U16(&msg, 4) = ari;
- RPC_U8(&msg, 6) = enable;
+ RPC_U8(&msg, 6) = (uint8_t) enable;
RPC_SIZE(&msg) = 3;
sc_call_rpc(ipc, &msg, false);
sc_rpc_msg_t msg;
RPC_VER(&msg) = SC_RPC_VERSION;
- RPC_SVC(&msg) = SC_RPC_SVC_MISC;
- RPC_FUNC(&msg) = MISC_FUNC_BOOT_STATUS;
+ RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_MISC;
+ RPC_FUNC(&msg) = (uint8_t) MISC_FUNC_BOOT_STATUS;
RPC_U8(&msg, 0) = status;
RPC_SIZE(&msg) = 2;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
- RPC_SVC(&msg) = SC_RPC_SVC_MISC;
- RPC_FUNC(&msg) = MISC_FUNC_BOOT_DONE;
+ RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_MISC;
+ RPC_FUNC(&msg) = (uint8_t) MISC_FUNC_BOOT_DONE;
RPC_U16(&msg, 0) = cpu;
RPC_SIZE(&msg) = 2;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
- RPC_SVC(&msg) = SC_RPC_SVC_MISC;
- RPC_FUNC(&msg) = MISC_FUNC_OTP_FUSE_READ;
+ RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_MISC;
+ RPC_FUNC(&msg) = (uint8_t) MISC_FUNC_OTP_FUSE_READ;
RPC_U32(&msg, 0) = word;
RPC_SIZE(&msg) = 2;
sc_call_rpc(ipc, &msg, false);
if (val != NULL)
+ {
*val = RPC_U32(&msg, 0);
+ }
+
+ result = RPC_R8(&msg);
+ return (sc_err_t) result;
+}
+
+sc_err_t sc_misc_otp_fuse_write(sc_ipc_t ipc, uint32_t word, uint32_t val)
+{
+ sc_rpc_msg_t msg;
+ uint8_t result;
+
+ RPC_VER(&msg) = SC_RPC_VERSION;
+ RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_MISC;
+ RPC_FUNC(&msg) = (uint8_t) MISC_FUNC_OTP_FUSE_WRITE;
+ RPC_U32(&msg, 0) = word;
+ RPC_U32(&msg, 4) = val;
+ RPC_SIZE(&msg) = 3;
+
+ sc_call_rpc(ipc, &msg, false);
+
result = RPC_R8(&msg);
return (sc_err_t) result;
}
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
- RPC_SVC(&msg) = SC_RPC_SVC_MISC;
- RPC_FUNC(&msg) = MISC_FUNC_SET_TEMP;
+ RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_MISC;
+ RPC_FUNC(&msg) = (uint8_t) MISC_FUNC_SET_TEMP;
RPC_U16(&msg, 0) = resource;
RPC_I16(&msg, 2) = celsius;
RPC_U8(&msg, 4) = temp;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
- RPC_SVC(&msg) = SC_RPC_SVC_MISC;
- RPC_FUNC(&msg) = MISC_FUNC_GET_TEMP;
+ RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_MISC;
+ RPC_FUNC(&msg) = (uint8_t) MISC_FUNC_GET_TEMP;
RPC_U16(&msg, 0) = resource;
RPC_U8(&msg, 2) = temp;
RPC_SIZE(&msg) = 2;
sc_call_rpc(ipc, &msg, false);
if (celsius != NULL)
+ {
*celsius = RPC_I16(&msg, 0);
+ }
+
result = RPC_R8(&msg);
if (tenths != NULL)
+ {
*tenths = RPC_I8(&msg, 2);
+ }
+
return (sc_err_t) result;
}
sc_rpc_msg_t msg;
RPC_VER(&msg) = SC_RPC_VERSION;
- RPC_SVC(&msg) = SC_RPC_SVC_MISC;
- RPC_FUNC(&msg) = MISC_FUNC_GET_BOOT_DEV;
+ RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_MISC;
+ RPC_FUNC(&msg) = (uint8_t) MISC_FUNC_GET_BOOT_DEV;
RPC_SIZE(&msg) = 1;
sc_call_rpc(ipc, &msg, false);
if (dev != NULL)
+ {
*dev = RPC_U16(&msg, 0);
+ }
+
+ return;
+}
+
+void sc_misc_get_button_status(sc_ipc_t ipc, bool *status)
+{
+ sc_rpc_msg_t msg;
+
+ RPC_VER(&msg) = SC_RPC_VERSION;
+ RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_MISC;
+ RPC_FUNC(&msg) = (uint8_t) MISC_FUNC_GET_BUTTON_STATUS;
+ RPC_SIZE(&msg) = 1;
+
+ sc_call_rpc(ipc, &msg, false);
+
+ if (status != NULL)
+ {
+ *status = RPC_U8(&msg, 0);
+ }
+
return;
}
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
- RPC_SVC(&msg) = SC_RPC_SVC_PAD;
- RPC_FUNC(&msg) = PAD_FUNC_SET_MUX;
+ RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_PAD;
+ RPC_FUNC(&msg) = (uint8_t) PAD_FUNC_SET_MUX;
RPC_U16(&msg, 0) = pad;
RPC_U8(&msg, 2) = mux;
RPC_U8(&msg, 3) = config;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
- RPC_SVC(&msg) = SC_RPC_SVC_PAD;
- RPC_FUNC(&msg) = PAD_FUNC_GET_MUX;
+ RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_PAD;
+ RPC_FUNC(&msg) = (uint8_t) PAD_FUNC_GET_MUX;
RPC_U16(&msg, 0) = pad;
RPC_SIZE(&msg) = 2;
result = RPC_R8(&msg);
if (mux != NULL)
+ {
*mux = RPC_U8(&msg, 0);
+ }
+
if (config != NULL)
+ {
*config = RPC_U8(&msg, 1);
+ }
+
if (iso != NULL)
+ {
*iso = RPC_U8(&msg, 2);
+ }
+
return (sc_err_t) result;
}
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
- RPC_SVC(&msg) = SC_RPC_SVC_PAD;
- RPC_FUNC(&msg) = PAD_FUNC_SET_GP;
+ RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_PAD;
+ RPC_FUNC(&msg) = (uint8_t) PAD_FUNC_SET_GP;
RPC_U32(&msg, 0) = ctrl;
RPC_U16(&msg, 4) = pad;
RPC_SIZE(&msg) = 3;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
- RPC_SVC(&msg) = SC_RPC_SVC_PAD;
- RPC_FUNC(&msg) = PAD_FUNC_GET_GP;
+ RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_PAD;
+ RPC_FUNC(&msg) = (uint8_t) PAD_FUNC_GET_GP;
RPC_U16(&msg, 0) = pad;
RPC_SIZE(&msg) = 2;
sc_call_rpc(ipc, &msg, false);
if (ctrl != NULL)
+ {
*ctrl = RPC_U32(&msg, 0);
+ }
+
result = RPC_R8(&msg);
return (sc_err_t) result;
}
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
- RPC_SVC(&msg) = SC_RPC_SVC_PAD;
- RPC_FUNC(&msg) = PAD_FUNC_SET_WAKEUP;
+ RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_PAD;
+ RPC_FUNC(&msg) = (uint8_t) PAD_FUNC_SET_WAKEUP;
RPC_U16(&msg, 0) = pad;
RPC_U8(&msg, 2) = wakeup;
RPC_SIZE(&msg) = 2;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
- RPC_SVC(&msg) = SC_RPC_SVC_PAD;
- RPC_FUNC(&msg) = PAD_FUNC_GET_WAKEUP;
+ RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_PAD;
+ RPC_FUNC(&msg) = (uint8_t) PAD_FUNC_GET_WAKEUP;
RPC_U16(&msg, 0) = pad;
RPC_SIZE(&msg) = 2;
result = RPC_R8(&msg);
if (wakeup != NULL)
+ {
*wakeup = RPC_U8(&msg, 0);
+ }
+
return (sc_err_t) result;
}
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
- RPC_SVC(&msg) = SC_RPC_SVC_PAD;
- RPC_FUNC(&msg) = PAD_FUNC_SET_ALL;
+ RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_PAD;
+ RPC_FUNC(&msg) = (uint8_t) PAD_FUNC_SET_ALL;
RPC_U32(&msg, 0) = ctrl;
RPC_U16(&msg, 4) = pad;
RPC_U8(&msg, 6) = mux;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
- RPC_SVC(&msg) = SC_RPC_SVC_PAD;
- RPC_FUNC(&msg) = PAD_FUNC_GET_ALL;
+ RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_PAD;
+ RPC_FUNC(&msg) = (uint8_t) PAD_FUNC_GET_ALL;
RPC_U16(&msg, 0) = pad;
RPC_SIZE(&msg) = 2;
sc_call_rpc(ipc, &msg, false);
if (ctrl != NULL)
+ {
*ctrl = RPC_U32(&msg, 0);
+ }
+
result = RPC_R8(&msg);
if (mux != NULL)
+ {
*mux = RPC_U8(&msg, 4);
+ }
+
if (config != NULL)
+ {
*config = RPC_U8(&msg, 5);
+ }
+
if (iso != NULL)
+ {
*iso = RPC_U8(&msg, 6);
+ }
+
if (wakeup != NULL)
+ {
*wakeup = RPC_U8(&msg, 7);
+ }
+
return (sc_err_t) result;
}
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
- RPC_SVC(&msg) = SC_RPC_SVC_PAD;
- RPC_FUNC(&msg) = PAD_FUNC_SET;
+ RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_PAD;
+ RPC_FUNC(&msg) = (uint8_t) PAD_FUNC_SET;
RPC_U32(&msg, 0) = val;
RPC_U16(&msg, 4) = pad;
RPC_SIZE(&msg) = 3;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
- RPC_SVC(&msg) = SC_RPC_SVC_PAD;
- RPC_FUNC(&msg) = PAD_FUNC_GET;
+ RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_PAD;
+ RPC_FUNC(&msg) = (uint8_t) PAD_FUNC_GET;
RPC_U16(&msg, 0) = pad;
RPC_SIZE(&msg) = 2;
sc_call_rpc(ipc, &msg, false);
if (val != NULL)
+ {
*val = RPC_U32(&msg, 0);
+ }
+
result = RPC_R8(&msg);
return (sc_err_t) result;
}
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
- RPC_SVC(&msg) = SC_RPC_SVC_PAD;
- RPC_FUNC(&msg) = PAD_FUNC_SET_GP_28FDSOI;
+ RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_PAD;
+ RPC_FUNC(&msg) = (uint8_t) PAD_FUNC_SET_GP_28FDSOI;
RPC_U16(&msg, 0) = pad;
RPC_U8(&msg, 2) = dse;
RPC_U8(&msg, 3) = ps;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
- RPC_SVC(&msg) = SC_RPC_SVC_PAD;
- RPC_FUNC(&msg) = PAD_FUNC_GET_GP_28FDSOI;
+ RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_PAD;
+ RPC_FUNC(&msg) = (uint8_t) PAD_FUNC_GET_GP_28FDSOI;
RPC_U16(&msg, 0) = pad;
RPC_SIZE(&msg) = 2;
result = RPC_R8(&msg);
if (dse != NULL)
+ {
*dse = RPC_U8(&msg, 0);
+ }
+
if (ps != NULL)
+ {
*ps = RPC_U8(&msg, 1);
+ }
+
return (sc_err_t) result;
}
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
- RPC_SVC(&msg) = SC_RPC_SVC_PAD;
- RPC_FUNC(&msg) = PAD_FUNC_SET_GP_28FDSOI_HSIC;
+ RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_PAD;
+ RPC_FUNC(&msg) = (uint8_t) PAD_FUNC_SET_GP_28FDSOI_HSIC;
RPC_U16(&msg, 0) = pad;
RPC_U8(&msg, 2) = dse;
RPC_U8(&msg, 3) = pus;
- RPC_U8(&msg, 4) = hys;
- RPC_U8(&msg, 5) = pke;
- RPC_U8(&msg, 6) = pue;
+ RPC_U8(&msg, 4) = (uint8_t) hys;
+ RPC_U8(&msg, 5) = (uint8_t) pke;
+ RPC_U8(&msg, 6) = (uint8_t) pue;
RPC_SIZE(&msg) = 3;
sc_call_rpc(ipc, &msg, false);
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
- RPC_SVC(&msg) = SC_RPC_SVC_PAD;
- RPC_FUNC(&msg) = PAD_FUNC_GET_GP_28FDSOI_HSIC;
+ RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_PAD;
+ RPC_FUNC(&msg) = (uint8_t) PAD_FUNC_GET_GP_28FDSOI_HSIC;
RPC_U16(&msg, 0) = pad;
RPC_SIZE(&msg) = 2;
result = RPC_R8(&msg);
if (dse != NULL)
+ {
*dse = RPC_U8(&msg, 0);
+ }
+
if (pus != NULL)
+ {
*pus = RPC_U8(&msg, 1);
+ }
+
if (hys != NULL)
+ {
*hys = RPC_U8(&msg, 2);
+ }
+
if (pke != NULL)
+ {
*pke = RPC_U8(&msg, 3);
+ }
+
if (pue != NULL)
+ {
*pue = RPC_U8(&msg, 4);
+ }
+
return (sc_err_t) result;
}
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
- RPC_SVC(&msg) = SC_RPC_SVC_PAD;
- RPC_FUNC(&msg) = PAD_FUNC_SET_GP_28FDSOI_COMP;
+ RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_PAD;
+ RPC_FUNC(&msg) = (uint8_t) PAD_FUNC_SET_GP_28FDSOI_COMP;
RPC_U16(&msg, 0) = pad;
RPC_U8(&msg, 2) = compen;
RPC_U8(&msg, 3) = rasrcp;
RPC_U8(&msg, 4) = rasrcn;
- RPC_U8(&msg, 5) = fastfrz;
- RPC_U8(&msg, 6) = nasrc_sel;
- RPC_U8(&msg, 7) = psw_ovr;
+ RPC_U8(&msg, 5) = (uint8_t) fastfrz;
+ RPC_U8(&msg, 6) = (uint8_t) nasrc_sel;
+ RPC_U8(&msg, 7) = (uint8_t) psw_ovr;
RPC_SIZE(&msg) = 3;
sc_call_rpc(ipc, &msg, false);
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
- RPC_SVC(&msg) = SC_RPC_SVC_PAD;
- RPC_FUNC(&msg) = PAD_FUNC_GET_GP_28FDSOI_COMP;
+ RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_PAD;
+ RPC_FUNC(&msg) = (uint8_t) PAD_FUNC_GET_GP_28FDSOI_COMP;
RPC_U16(&msg, 0) = pad;
RPC_SIZE(&msg) = 2;
result = RPC_R8(&msg);
if (compen != NULL)
+ {
*compen = RPC_U8(&msg, 0);
+ }
+
if (rasrcp != NULL)
+ {
*rasrcp = RPC_U8(&msg, 1);
+ }
+
if (rasrcn != NULL)
+ {
*rasrcn = RPC_U8(&msg, 2);
+ }
+
if (nasrc != NULL)
+ {
*nasrc = RPC_U8(&msg, 3);
+ }
+
if (fastfrz != NULL)
+ {
*fastfrz = RPC_U8(&msg, 4);
+ }
+
if (nasrc_sel != NULL)
+ {
*nasrc_sel = RPC_U8(&msg, 5);
+ }
+
if (compok != NULL)
+ {
*compok = RPC_U8(&msg, 6);
+ }
+
if (psw_ovr != NULL)
+ {
*psw_ovr = RPC_U8(&msg, 7);
+ }
+
return (sc_err_t) result;
}
typedef enum pm_func_e
{
PM_FUNC_UNKNOWN = 0, /*!< Unknown function */
- PM_FUNC_SET_SYS_POWER_MODE = 1, /*!< Index for pm_set_sys_power_mode() RPC call */
+ PM_FUNC_SET_SYS_POWER_MODE = 19, /*!< Index for pm_set_sys_power_mode() RPC call */
+ PM_FUNC_SET_PARTITION_POWER_MODE = 1, /*!< Index for pm_set_partition_power_mode() RPC call */
PM_FUNC_GET_SYS_POWER_MODE = 2, /*!< Index for pm_get_sys_power_mode() RPC call */
PM_FUNC_SET_RESOURCE_POWER_MODE = 3, /*!< Index for pm_set_resource_power_mode() RPC call */
PM_FUNC_GET_RESOURCE_POWER_MODE = 4, /*!< Index for pm_get_resource_power_mode() RPC call */
+ PM_FUNC_REQ_LOW_POWER_MODE = 16, /*!< Index for pm_req_low_power_mode() RPC call */
+ PM_FUNC_SET_CPU_RESUME_ADDR = 17, /*!< Index for pm_set_cpu_resume_addr() RPC call */
+ PM_FUNC_REQ_SYS_IF_POWER_MODE = 18, /*!< Index for pm_req_sys_if_power_mode() RPC call */
PM_FUNC_SET_CLOCK_RATE = 5, /*!< Index for pm_set_clock_rate() RPC call */
PM_FUNC_GET_CLOCK_RATE = 6, /*!< Index for pm_get_clock_rate() RPC call */
PM_FUNC_CLOCK_ENABLE = 7, /*!< Index for pm_clock_enable() RPC call */
/* Local Functions */
-sc_err_t sc_pm_set_sys_power_mode(sc_ipc_t ipc, sc_rm_pt_t pt,
+sc_err_t sc_pm_set_sys_power_mode(sc_ipc_t ipc, sc_pm_power_mode_t mode)
+{
+ sc_rpc_msg_t msg;
+ uint8_t result;
+
+ RPC_VER(&msg) = SC_RPC_VERSION;
+ RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_PM;
+ RPC_FUNC(&msg) = (uint8_t) PM_FUNC_SET_SYS_POWER_MODE;
+ RPC_U8(&msg, 0) = mode;
+ RPC_SIZE(&msg) = 2;
+
+ sc_call_rpc(ipc, &msg, false);
+
+ result = RPC_R8(&msg);
+ return (sc_err_t) result;
+}
+
+sc_err_t sc_pm_set_partition_power_mode(sc_ipc_t ipc, sc_rm_pt_t pt,
sc_pm_power_mode_t mode)
{
sc_rpc_msg_t msg;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
- RPC_SVC(&msg) = SC_RPC_SVC_PM;
- RPC_FUNC(&msg) = PM_FUNC_SET_SYS_POWER_MODE;
+ RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_PM;
+ RPC_FUNC(&msg) = (uint8_t) PM_FUNC_SET_PARTITION_POWER_MODE;
RPC_U8(&msg, 0) = pt;
RPC_U8(&msg, 1) = mode;
RPC_SIZE(&msg) = 2;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
- RPC_SVC(&msg) = SC_RPC_SVC_PM;
- RPC_FUNC(&msg) = PM_FUNC_GET_SYS_POWER_MODE;
+ RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_PM;
+ RPC_FUNC(&msg) = (uint8_t) PM_FUNC_GET_SYS_POWER_MODE;
RPC_U8(&msg, 0) = pt;
RPC_SIZE(&msg) = 2;
result = RPC_R8(&msg);
if (mode != NULL)
+ {
*mode = RPC_U8(&msg, 0);
+ }
+
return (sc_err_t) result;
}
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
- RPC_SVC(&msg) = SC_RPC_SVC_PM;
- RPC_FUNC(&msg) = PM_FUNC_SET_RESOURCE_POWER_MODE;
+ RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_PM;
+ RPC_FUNC(&msg) = (uint8_t) PM_FUNC_SET_RESOURCE_POWER_MODE;
RPC_U16(&msg, 0) = resource;
RPC_U8(&msg, 2) = mode;
RPC_SIZE(&msg) = 2;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
- RPC_SVC(&msg) = SC_RPC_SVC_PM;
- RPC_FUNC(&msg) = PM_FUNC_GET_RESOURCE_POWER_MODE;
+ RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_PM;
+ RPC_FUNC(&msg) = (uint8_t) PM_FUNC_GET_RESOURCE_POWER_MODE;
RPC_U16(&msg, 0) = resource;
RPC_SIZE(&msg) = 2;
result = RPC_R8(&msg);
if (mode != NULL)
+ {
*mode = RPC_U8(&msg, 0);
+ }
+
+ return (sc_err_t) result;
+}
+
+sc_err_t sc_pm_req_low_power_mode(sc_ipc_t ipc, sc_rsrc_t resource,
+ sc_pm_power_mode_t mode)
+{
+ sc_rpc_msg_t msg;
+ uint8_t result;
+
+ RPC_VER(&msg) = SC_RPC_VERSION;
+ RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_PM;
+ RPC_FUNC(&msg) = (uint8_t) PM_FUNC_REQ_LOW_POWER_MODE;
+ RPC_U16(&msg, 0) = resource;
+ RPC_U8(&msg, 2) = mode;
+ RPC_SIZE(&msg) = 2;
+
+ sc_call_rpc(ipc, &msg, false);
+
+ result = RPC_R8(&msg);
+ return (sc_err_t) result;
+}
+
+sc_err_t sc_pm_set_cpu_resume_addr(sc_ipc_t ipc, sc_rsrc_t resource,
+ sc_faddr_t address)
+{
+ sc_rpc_msg_t msg;
+ uint8_t result;
+
+ RPC_VER(&msg) = SC_RPC_VERSION;
+ RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_PM;
+ RPC_FUNC(&msg) = (uint8_t) PM_FUNC_SET_CPU_RESUME_ADDR;
+ RPC_U32(&msg, 0) = (uint32_t) (address >> 32u);
+ RPC_U32(&msg, 4) = (uint32_t) address;
+ RPC_U16(&msg, 8) = resource;
+ RPC_SIZE(&msg) = 4;
+
+ sc_call_rpc(ipc, &msg, false);
+
+ result = RPC_R8(&msg);
+ return (sc_err_t) result;
+}
+
+sc_err_t sc_pm_req_sys_if_power_mode(sc_ipc_t ipc, sc_rsrc_t resource,
+ sc_pm_sys_if_t sys_if, sc_pm_power_mode_t hpm, sc_pm_power_mode_t lpm)
+{
+ sc_rpc_msg_t msg;
+ uint8_t result;
+
+ RPC_VER(&msg) = SC_RPC_VERSION;
+ RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_PM;
+ RPC_FUNC(&msg) = (uint8_t) PM_FUNC_REQ_SYS_IF_POWER_MODE;
+ RPC_U16(&msg, 0) = resource;
+ RPC_U8(&msg, 2) = sys_if;
+ RPC_U8(&msg, 3) = hpm;
+ RPC_U8(&msg, 4) = lpm;
+ RPC_SIZE(&msg) = 3;
+
+ sc_call_rpc(ipc, &msg, false);
+
+ result = RPC_R8(&msg);
return (sc_err_t) result;
}
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
- RPC_SVC(&msg) = SC_RPC_SVC_PM;
- RPC_FUNC(&msg) = PM_FUNC_SET_CLOCK_RATE;
+ RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_PM;
+ RPC_FUNC(&msg) = (uint8_t) PM_FUNC_SET_CLOCK_RATE;
RPC_U32(&msg, 0) = *rate;
RPC_U16(&msg, 4) = resource;
RPC_U8(&msg, 6) = clk;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
- RPC_SVC(&msg) = SC_RPC_SVC_PM;
- RPC_FUNC(&msg) = PM_FUNC_GET_CLOCK_RATE;
+ RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_PM;
+ RPC_FUNC(&msg) = (uint8_t) PM_FUNC_GET_CLOCK_RATE;
RPC_U16(&msg, 0) = resource;
RPC_U8(&msg, 2) = clk;
RPC_SIZE(&msg) = 2;
sc_call_rpc(ipc, &msg, false);
if (rate != NULL)
+ {
*rate = RPC_U32(&msg, 0);
+ }
+
result = RPC_R8(&msg);
return (sc_err_t) result;
}
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
- RPC_SVC(&msg) = SC_RPC_SVC_PM;
- RPC_FUNC(&msg) = PM_FUNC_CLOCK_ENABLE;
+ RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_PM;
+ RPC_FUNC(&msg) = (uint8_t) PM_FUNC_CLOCK_ENABLE;
RPC_U16(&msg, 0) = resource;
RPC_U8(&msg, 2) = clk;
- RPC_U8(&msg, 3) = enable;
- RPC_U8(&msg, 4) = autog;
+ RPC_U8(&msg, 3) = (uint8_t) enable;
+ RPC_U8(&msg, 4) = (uint8_t) autog;
RPC_SIZE(&msg) = 3;
sc_call_rpc(ipc, &msg, false);
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
- RPC_SVC(&msg) = SC_RPC_SVC_PM;
- RPC_FUNC(&msg) = PM_FUNC_SET_CLOCK_PARENT;
+ RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_PM;
+ RPC_FUNC(&msg) = (uint8_t) PM_FUNC_SET_CLOCK_PARENT;
RPC_U16(&msg, 0) = resource;
RPC_U8(&msg, 2) = clk;
RPC_U8(&msg, 3) = parent;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
- RPC_SVC(&msg) = SC_RPC_SVC_PM;
- RPC_FUNC(&msg) = PM_FUNC_GET_CLOCK_PARENT;
+ RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_PM;
+ RPC_FUNC(&msg) = (uint8_t) PM_FUNC_GET_CLOCK_PARENT;
RPC_U16(&msg, 0) = resource;
RPC_U8(&msg, 2) = clk;
RPC_SIZE(&msg) = 2;
result = RPC_R8(&msg);
if (parent != NULL)
+ {
*parent = RPC_U8(&msg, 0);
+ }
+
return (sc_err_t) result;
}
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
- RPC_SVC(&msg) = SC_RPC_SVC_PM;
- RPC_FUNC(&msg) = PM_FUNC_RESET;
+ RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_PM;
+ RPC_FUNC(&msg) = (uint8_t) PM_FUNC_RESET;
RPC_U8(&msg, 0) = type;
RPC_SIZE(&msg) = 2;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
- RPC_SVC(&msg) = SC_RPC_SVC_PM;
- RPC_FUNC(&msg) = PM_FUNC_RESET_REASON;
+ RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_PM;
+ RPC_FUNC(&msg) = (uint8_t) PM_FUNC_RESET_REASON;
RPC_SIZE(&msg) = 1;
sc_call_rpc(ipc, &msg, false);
result = RPC_R8(&msg);
if (reason != NULL)
+ {
*reason = RPC_U8(&msg, 0);
+ }
+
return (sc_err_t) result;
}
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
- RPC_SVC(&msg) = SC_RPC_SVC_PM;
- RPC_FUNC(&msg) = PM_FUNC_BOOT;
- RPC_U32(&msg, 0) = boot_addr >> 32;
- RPC_U32(&msg, 4) = boot_addr;
+ RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_PM;
+ RPC_FUNC(&msg) = (uint8_t) PM_FUNC_BOOT;
+ RPC_U32(&msg, 0) = (uint32_t) (boot_addr >> 32u);
+ RPC_U32(&msg, 4) = (uint32_t) boot_addr;
RPC_U16(&msg, 8) = resource_cpu;
RPC_U16(&msg, 10) = resource_mu;
RPC_U16(&msg, 12) = resource_dev;
sc_rpc_msg_t msg;
RPC_VER(&msg) = SC_RPC_VERSION;
- RPC_SVC(&msg) = SC_RPC_SVC_PM;
- RPC_FUNC(&msg) = PM_FUNC_REBOOT;
+ RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_PM;
+ RPC_FUNC(&msg) = (uint8_t) PM_FUNC_REBOOT;
RPC_U8(&msg, 0) = type;
RPC_SIZE(&msg) = 2;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
- RPC_SVC(&msg) = SC_RPC_SVC_PM;
- RPC_FUNC(&msg) = PM_FUNC_REBOOT_PARTITION;
+ RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_PM;
+ RPC_FUNC(&msg) = (uint8_t) PM_FUNC_REBOOT_PARTITION;
RPC_U8(&msg, 0) = pt;
RPC_U8(&msg, 1) = type;
RPC_SIZE(&msg) = 2;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
- RPC_SVC(&msg) = SC_RPC_SVC_PM;
- RPC_FUNC(&msg) = PM_FUNC_CPU_START;
- RPC_U32(&msg, 0) = address >> 32;
- RPC_U32(&msg, 4) = address;
+ RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_PM;
+ RPC_FUNC(&msg) = (uint8_t) PM_FUNC_CPU_START;
+ RPC_U32(&msg, 0) = (uint32_t) (address >> 32u);
+ RPC_U32(&msg, 4) = (uint32_t) address;
RPC_U16(&msg, 8) = resource;
- RPC_U8(&msg, 10) = enable;
+ RPC_U8(&msg, 10) = (uint8_t) enable;
RPC_SIZE(&msg) = 4;
sc_call_rpc(ipc, &msg, false);
{
RM_FUNC_UNKNOWN = 0, /*!< Unknown function */
RM_FUNC_PARTITION_ALLOC = 1, /*!< Index for rm_partition_alloc() RPC call */
+ RM_FUNC_SET_CONFIDENTIAL = 31, /*!< Index for rm_set_confidential() RPC call */
RM_FUNC_PARTITION_FREE = 2, /*!< Index for rm_partition_free() RPC call */
RM_FUNC_GET_DID = 26, /*!< Index for rm_get_did() RPC call */
RM_FUNC_PARTITION_STATIC = 3, /*!< Index for rm_partition_static() RPC call */
/* Local Functions */
sc_err_t sc_rm_partition_alloc(sc_ipc_t ipc, sc_rm_pt_t *pt, bool secure,
- bool isolated, bool restricted, bool confidential, bool coherent)
+ bool isolated, bool restricted, bool grant, bool coherent)
{
sc_rpc_msg_t msg;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
- RPC_SVC(&msg) = SC_RPC_SVC_RM;
- RPC_FUNC(&msg) = RM_FUNC_PARTITION_ALLOC;
- RPC_U8(&msg, 0) = secure;
- RPC_U8(&msg, 1) = isolated;
- RPC_U8(&msg, 2) = restricted;
- RPC_U8(&msg, 3) = confidential;
- RPC_U8(&msg, 4) = coherent;
+ RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_RM;
+ RPC_FUNC(&msg) = (uint8_t) RM_FUNC_PARTITION_ALLOC;
+ RPC_U8(&msg, 0) = (uint8_t) secure;
+ RPC_U8(&msg, 1) = (uint8_t) isolated;
+ RPC_U8(&msg, 2) = (uint8_t) restricted;
+ RPC_U8(&msg, 3) = (uint8_t) grant;
+ RPC_U8(&msg, 4) = (uint8_t) coherent;
RPC_SIZE(&msg) = 3;
sc_call_rpc(ipc, &msg, false);
result = RPC_R8(&msg);
if (pt != NULL)
+ {
*pt = RPC_U8(&msg, 0);
+ }
+
+ return (sc_err_t) result;
+}
+
+sc_err_t sc_rm_set_confidential(sc_ipc_t ipc, sc_rm_pt_t pt, bool retro)
+{
+ sc_rpc_msg_t msg;
+ uint8_t result;
+
+ RPC_VER(&msg) = SC_RPC_VERSION;
+ RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_RM;
+ RPC_FUNC(&msg) = (uint8_t) RM_FUNC_SET_CONFIDENTIAL;
+ RPC_U8(&msg, 0) = pt;
+ RPC_U8(&msg, 1) = (uint8_t) retro;
+ RPC_SIZE(&msg) = 2;
+
+ sc_call_rpc(ipc, &msg, false);
+
+ result = RPC_R8(&msg);
return (sc_err_t) result;
}
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
- RPC_SVC(&msg) = SC_RPC_SVC_RM;
- RPC_FUNC(&msg) = RM_FUNC_PARTITION_FREE;
+ RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_RM;
+ RPC_FUNC(&msg) = (uint8_t) RM_FUNC_PARTITION_FREE;
RPC_U8(&msg, 0) = pt;
RPC_SIZE(&msg) = 2;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
- RPC_SVC(&msg) = SC_RPC_SVC_RM;
- RPC_FUNC(&msg) = RM_FUNC_GET_DID;
+ RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_RM;
+ RPC_FUNC(&msg) = (uint8_t) RM_FUNC_GET_DID;
RPC_SIZE(&msg) = 1;
sc_call_rpc(ipc, &msg, false);
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
- RPC_SVC(&msg) = SC_RPC_SVC_RM;
- RPC_FUNC(&msg) = RM_FUNC_PARTITION_STATIC;
+ RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_RM;
+ RPC_FUNC(&msg) = (uint8_t) RM_FUNC_PARTITION_STATIC;
RPC_U8(&msg, 0) = pt;
RPC_U8(&msg, 1) = did;
RPC_SIZE(&msg) = 2;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
- RPC_SVC(&msg) = SC_RPC_SVC_RM;
- RPC_FUNC(&msg) = RM_FUNC_PARTITION_LOCK;
+ RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_RM;
+ RPC_FUNC(&msg) = (uint8_t) RM_FUNC_PARTITION_LOCK;
RPC_U8(&msg, 0) = pt;
RPC_SIZE(&msg) = 2;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
- RPC_SVC(&msg) = SC_RPC_SVC_RM;
- RPC_FUNC(&msg) = RM_FUNC_GET_PARTITION;
+ RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_RM;
+ RPC_FUNC(&msg) = (uint8_t) RM_FUNC_GET_PARTITION;
RPC_SIZE(&msg) = 1;
sc_call_rpc(ipc, &msg, false);
result = RPC_R8(&msg);
if (pt != NULL)
+ {
*pt = RPC_U8(&msg, 0);
+ }
+
return (sc_err_t) result;
}
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
- RPC_SVC(&msg) = SC_RPC_SVC_RM;
- RPC_FUNC(&msg) = RM_FUNC_SET_PARENT;
+ RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_RM;
+ RPC_FUNC(&msg) = (uint8_t) RM_FUNC_SET_PARENT;
RPC_U8(&msg, 0) = pt;
RPC_U8(&msg, 1) = pt_parent;
RPC_SIZE(&msg) = 2;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
- RPC_SVC(&msg) = SC_RPC_SVC_RM;
- RPC_FUNC(&msg) = RM_FUNC_MOVE_ALL;
+ RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_RM;
+ RPC_FUNC(&msg) = (uint8_t) RM_FUNC_MOVE_ALL;
RPC_U8(&msg, 0) = pt_src;
RPC_U8(&msg, 1) = pt_dst;
- RPC_U8(&msg, 2) = move_rsrc;
- RPC_U8(&msg, 3) = move_pads;
+ RPC_U8(&msg, 2) = (uint8_t) move_rsrc;
+ RPC_U8(&msg, 3) = (uint8_t) move_pads;
RPC_SIZE(&msg) = 2;
sc_call_rpc(ipc, &msg, false);
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
- RPC_SVC(&msg) = SC_RPC_SVC_RM;
- RPC_FUNC(&msg) = RM_FUNC_ASSIGN_RESOURCE;
+ RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_RM;
+ RPC_FUNC(&msg) = (uint8_t) RM_FUNC_ASSIGN_RESOURCE;
RPC_U16(&msg, 0) = resource;
RPC_U8(&msg, 2) = pt;
RPC_SIZE(&msg) = 2;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
- RPC_SVC(&msg) = SC_RPC_SVC_RM;
- RPC_FUNC(&msg) = RM_FUNC_SET_RESOURCE_MOVABLE;
+ RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_RM;
+ RPC_FUNC(&msg) = (uint8_t) RM_FUNC_SET_RESOURCE_MOVABLE;
RPC_U16(&msg, 0) = resource_fst;
RPC_U16(&msg, 2) = resource_lst;
- RPC_U8(&msg, 4) = movable;
+ RPC_U8(&msg, 4) = (uint8_t) movable;
RPC_SIZE(&msg) = 3;
sc_call_rpc(ipc, &msg, false);
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
- RPC_SVC(&msg) = SC_RPC_SVC_RM;
- RPC_FUNC(&msg) = RM_FUNC_SET_SUBSYS_RSRC_MOVABLE;
+ RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_RM;
+ RPC_FUNC(&msg) = (uint8_t) RM_FUNC_SET_SUBSYS_RSRC_MOVABLE;
RPC_U16(&msg, 0) = resource;
- RPC_U8(&msg, 2) = movable;
+ RPC_U8(&msg, 2) = (uint8_t) movable;
RPC_SIZE(&msg) = 2;
sc_call_rpc(ipc, &msg, false);
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
- RPC_SVC(&msg) = SC_RPC_SVC_RM;
- RPC_FUNC(&msg) = RM_FUNC_SET_MASTER_ATTRIBUTES;
+ RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_RM;
+ RPC_FUNC(&msg) = (uint8_t) RM_FUNC_SET_MASTER_ATTRIBUTES;
RPC_U16(&msg, 0) = resource;
RPC_U8(&msg, 2) = sa;
RPC_U8(&msg, 3) = pa;
- RPC_U8(&msg, 4) = smmu_bypass;
+ RPC_U8(&msg, 4) = (uint8_t) smmu_bypass;
RPC_SIZE(&msg) = 3;
sc_call_rpc(ipc, &msg, false);
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
- RPC_SVC(&msg) = SC_RPC_SVC_RM;
- RPC_FUNC(&msg) = RM_FUNC_SET_MASTER_SID;
+ RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_RM;
+ RPC_FUNC(&msg) = (uint8_t) RM_FUNC_SET_MASTER_SID;
RPC_U16(&msg, 0) = resource;
RPC_U16(&msg, 2) = sid;
RPC_SIZE(&msg) = 2;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
- RPC_SVC(&msg) = SC_RPC_SVC_RM;
- RPC_FUNC(&msg) = RM_FUNC_SET_PERIPHERAL_PERMISSIONS;
+ RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_RM;
+ RPC_FUNC(&msg) = (uint8_t) RM_FUNC_SET_PERIPHERAL_PERMISSIONS;
RPC_U16(&msg, 0) = resource;
RPC_U8(&msg, 2) = pt;
RPC_U8(&msg, 3) = perm;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
- RPC_SVC(&msg) = SC_RPC_SVC_RM;
- RPC_FUNC(&msg) = RM_FUNC_IS_RESOURCE_OWNED;
+ RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_RM;
+ RPC_FUNC(&msg) = (uint8_t) RM_FUNC_IS_RESOURCE_OWNED;
RPC_U16(&msg, 0) = resource;
RPC_SIZE(&msg) = 2;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
- RPC_SVC(&msg) = SC_RPC_SVC_RM;
- RPC_FUNC(&msg) = RM_FUNC_IS_RESOURCE_MASTER;
+ RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_RM;
+ RPC_FUNC(&msg) = (uint8_t) RM_FUNC_IS_RESOURCE_MASTER;
RPC_U16(&msg, 0) = resource;
RPC_SIZE(&msg) = 2;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
- RPC_SVC(&msg) = SC_RPC_SVC_RM;
- RPC_FUNC(&msg) = RM_FUNC_IS_RESOURCE_PERIPHERAL;
+ RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_RM;
+ RPC_FUNC(&msg) = (uint8_t) RM_FUNC_IS_RESOURCE_PERIPHERAL;
RPC_U16(&msg, 0) = resource;
RPC_SIZE(&msg) = 2;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
- RPC_SVC(&msg) = SC_RPC_SVC_RM;
- RPC_FUNC(&msg) = RM_FUNC_GET_RESOURCE_INFO;
+ RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_RM;
+ RPC_FUNC(&msg) = (uint8_t) RM_FUNC_GET_RESOURCE_INFO;
RPC_U16(&msg, 0) = resource;
RPC_SIZE(&msg) = 2;
sc_call_rpc(ipc, &msg, false);
if (sid != NULL)
+ {
*sid = RPC_U16(&msg, 0);
+ }
+
result = RPC_R8(&msg);
return (sc_err_t) result;
}
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
- RPC_SVC(&msg) = SC_RPC_SVC_RM;
- RPC_FUNC(&msg) = RM_FUNC_MEMREG_ALLOC;
- RPC_U32(&msg, 0) = addr_start >> 32;
- RPC_U32(&msg, 4) = addr_start;
- RPC_U32(&msg, 8) = addr_end >> 32;
- RPC_U32(&msg, 12) = addr_end;
+ RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_RM;
+ RPC_FUNC(&msg) = (uint8_t) RM_FUNC_MEMREG_ALLOC;
+ RPC_U32(&msg, 0) = (uint32_t) (addr_start >> 32u);
+ RPC_U32(&msg, 4) = (uint32_t) addr_start;
+ RPC_U32(&msg, 8) = (uint32_t) (addr_end >> 32u);
+ RPC_U32(&msg, 12) = (uint32_t) addr_end;
RPC_SIZE(&msg) = 5;
sc_call_rpc(ipc, &msg, false);
result = RPC_R8(&msg);
if (mr != NULL)
+ {
*mr = RPC_U8(&msg, 0);
+ }
+
return (sc_err_t) result;
}
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
- RPC_SVC(&msg) = SC_RPC_SVC_RM;
- RPC_FUNC(&msg) = RM_FUNC_MEMREG_SPLIT;
- RPC_U32(&msg, 0) = addr_start >> 32;
- RPC_U32(&msg, 4) = addr_start;
- RPC_U32(&msg, 8) = addr_end >> 32;
- RPC_U32(&msg, 12) = addr_end;
+ RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_RM;
+ RPC_FUNC(&msg) = (uint8_t) RM_FUNC_MEMREG_SPLIT;
+ RPC_U32(&msg, 0) = (uint32_t) (addr_start >> 32u);
+ RPC_U32(&msg, 4) = (uint32_t) addr_start;
+ RPC_U32(&msg, 8) = (uint32_t) (addr_end >> 32u);
+ RPC_U32(&msg, 12) = (uint32_t) addr_end;
RPC_U8(&msg, 16) = mr;
RPC_SIZE(&msg) = 6;
result = RPC_R8(&msg);
if (mr_ret != NULL)
+ {
*mr_ret = RPC_U8(&msg, 0);
+ }
+
return (sc_err_t) result;
}
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
- RPC_SVC(&msg) = SC_RPC_SVC_RM;
- RPC_FUNC(&msg) = RM_FUNC_MEMREG_FREE;
+ RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_RM;
+ RPC_FUNC(&msg) = (uint8_t) RM_FUNC_MEMREG_FREE;
RPC_U8(&msg, 0) = mr;
RPC_SIZE(&msg) = 2;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
- RPC_SVC(&msg) = SC_RPC_SVC_RM;
- RPC_FUNC(&msg) = RM_FUNC_FIND_MEMREG;
- RPC_U32(&msg, 0) = addr_start >> 32;
- RPC_U32(&msg, 4) = addr_start;
- RPC_U32(&msg, 8) = addr_end >> 32;
- RPC_U32(&msg, 12) = addr_end;
+ RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_RM;
+ RPC_FUNC(&msg) = (uint8_t) RM_FUNC_FIND_MEMREG;
+ RPC_U32(&msg, 0) = (uint32_t) (addr_start >> 32u);
+ RPC_U32(&msg, 4) = (uint32_t) addr_start;
+ RPC_U32(&msg, 8) = (uint32_t) (addr_end >> 32u);
+ RPC_U32(&msg, 12) = (uint32_t) addr_end;
RPC_SIZE(&msg) = 5;
sc_call_rpc(ipc, &msg, false);
result = RPC_R8(&msg);
if (mr != NULL)
+ {
*mr = RPC_U8(&msg, 0);
+ }
+
return (sc_err_t) result;
}
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
- RPC_SVC(&msg) = SC_RPC_SVC_RM;
- RPC_FUNC(&msg) = RM_FUNC_ASSIGN_MEMREG;
+ RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_RM;
+ RPC_FUNC(&msg) = (uint8_t) RM_FUNC_ASSIGN_MEMREG;
RPC_U8(&msg, 0) = pt;
RPC_U8(&msg, 1) = mr;
RPC_SIZE(&msg) = 2;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
- RPC_SVC(&msg) = SC_RPC_SVC_RM;
- RPC_FUNC(&msg) = RM_FUNC_SET_MEMREG_PERMISSIONS;
+ RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_RM;
+ RPC_FUNC(&msg) = (uint8_t) RM_FUNC_SET_MEMREG_PERMISSIONS;
RPC_U8(&msg, 0) = mr;
RPC_U8(&msg, 1) = pt;
RPC_U8(&msg, 2) = perm;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
- RPC_SVC(&msg) = SC_RPC_SVC_RM;
- RPC_FUNC(&msg) = RM_FUNC_IS_MEMREG_OWNED;
+ RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_RM;
+ RPC_FUNC(&msg) = (uint8_t) RM_FUNC_IS_MEMREG_OWNED;
RPC_U8(&msg, 0) = mr;
RPC_SIZE(&msg) = 2;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
- RPC_SVC(&msg) = SC_RPC_SVC_RM;
- RPC_FUNC(&msg) = RM_FUNC_GET_MEMREG_INFO;
+ RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_RM;
+ RPC_FUNC(&msg) = (uint8_t) RM_FUNC_GET_MEMREG_INFO;
RPC_U8(&msg, 0) = mr;
RPC_SIZE(&msg) = 2;
sc_call_rpc(ipc, &msg, false);
if (addr_start != NULL)
- *addr_start = ((uint64_t) RPC_U32(&msg, 0) << 32) | RPC_U32(&msg, 4);
+ {
+ *addr_start = ((uint64_t) RPC_U32(&msg, 0) << 32u) | RPC_U32(&msg, 4);
+ }
+
if (addr_end != NULL)
- *addr_end = ((uint64_t) RPC_U32(&msg, 8) << 32) | RPC_U32(&msg, 12);
+ {
+ *addr_end = ((uint64_t) RPC_U32(&msg, 8) << 32u) | RPC_U32(&msg, 12);
+ }
+
result = RPC_R8(&msg);
return (sc_err_t) result;
}
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
- RPC_SVC(&msg) = SC_RPC_SVC_RM;
- RPC_FUNC(&msg) = RM_FUNC_ASSIGN_PAD;
+ RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_RM;
+ RPC_FUNC(&msg) = (uint8_t) RM_FUNC_ASSIGN_PAD;
RPC_U16(&msg, 0) = pad;
RPC_U8(&msg, 2) = pt;
RPC_SIZE(&msg) = 2;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
- RPC_SVC(&msg) = SC_RPC_SVC_RM;
- RPC_FUNC(&msg) = RM_FUNC_SET_PAD_MOVABLE;
+ RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_RM;
+ RPC_FUNC(&msg) = (uint8_t) RM_FUNC_SET_PAD_MOVABLE;
RPC_U16(&msg, 0) = pad_fst;
RPC_U16(&msg, 2) = pad_lst;
- RPC_U8(&msg, 4) = movable;
+ RPC_U8(&msg, 4) = (uint8_t) movable;
RPC_SIZE(&msg) = 3;
sc_call_rpc(ipc, &msg, false);
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
- RPC_SVC(&msg) = SC_RPC_SVC_RM;
- RPC_FUNC(&msg) = RM_FUNC_IS_PAD_OWNED;
+ RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_RM;
+ RPC_FUNC(&msg) = (uint8_t) RM_FUNC_IS_PAD_OWNED;
RPC_U8(&msg, 0) = pad;
RPC_SIZE(&msg) = 2;
sc_rpc_msg_t msg;
RPC_VER(&msg) = SC_RPC_VERSION;
- RPC_SVC(&msg) = SC_RPC_SVC_RM;
- RPC_FUNC(&msg) = RM_FUNC_DUMP;
+ RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_RM;
+ RPC_FUNC(&msg) = (uint8_t) RM_FUNC_DUMP;
RPC_SIZE(&msg) = 1;
sc_call_rpc(ipc, &msg, false);
{
TIMER_FUNC_UNKNOWN = 0, /*!< Unknown function */
TIMER_FUNC_SET_WDOG_TIMEOUT = 1, /*!< Index for timer_set_wdog_timeout() RPC call */
+ TIMER_FUNC_SET_WDOG_PRE_TIMEOUT = 12, /*!< Index for timer_set_wdog_pre_timeout() RPC call */
TIMER_FUNC_START_WDOG = 2, /*!< Index for timer_start_wdog() RPC call */
TIMER_FUNC_STOP_WDOG = 3, /*!< Index for timer_stop_wdog() RPC call */
TIMER_FUNC_PING_WDOG = 4, /*!< Index for timer_ping_wdog() RPC call */
TIMER_FUNC_GET_WDOG_STATUS = 5, /*!< Index for timer_get_wdog_status() RPC call */
+ TIMER_FUNC_PT_GET_WDOG_STATUS = 13, /*!< Index for timer_pt_get_wdog_status() RPC call */
TIMER_FUNC_SET_WDOG_ACTION = 10, /*!< Index for timer_set_wdog_action() RPC call */
TIMER_FUNC_SET_RTC_TIME = 6, /*!< Index for timer_set_rtc_time() RPC call */
TIMER_FUNC_GET_RTC_TIME = 7, /*!< Index for timer_get_rtc_time() RPC call */
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
- RPC_SVC(&msg) = SC_RPC_SVC_TIMER;
- RPC_FUNC(&msg) = TIMER_FUNC_SET_WDOG_TIMEOUT;
+ RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_TIMER;
+ RPC_FUNC(&msg) = (uint8_t) TIMER_FUNC_SET_WDOG_TIMEOUT;
RPC_U32(&msg, 0) = timeout;
RPC_SIZE(&msg) = 2;
return (sc_err_t) result;
}
+sc_err_t sc_timer_set_wdog_pre_timeout(sc_ipc_t ipc,
+ sc_timer_wdog_time_t pre_timeout)
+{
+ sc_rpc_msg_t msg;
+ uint8_t result;
+
+ RPC_VER(&msg) = SC_RPC_VERSION;
+ RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_TIMER;
+ RPC_FUNC(&msg) = (uint8_t) TIMER_FUNC_SET_WDOG_PRE_TIMEOUT;
+ RPC_U32(&msg, 0) = pre_timeout;
+ RPC_SIZE(&msg) = 2;
+
+ sc_call_rpc(ipc, &msg, false);
+
+ result = RPC_R8(&msg);
+ return (sc_err_t) result;
+}
+
sc_err_t sc_timer_start_wdog(sc_ipc_t ipc, bool lock)
{
sc_rpc_msg_t msg;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
- RPC_SVC(&msg) = SC_RPC_SVC_TIMER;
- RPC_FUNC(&msg) = TIMER_FUNC_START_WDOG;
- RPC_U8(&msg, 0) = lock;
+ RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_TIMER;
+ RPC_FUNC(&msg) = (uint8_t) TIMER_FUNC_START_WDOG;
+ RPC_U8(&msg, 0) = (uint8_t) lock;
RPC_SIZE(&msg) = 2;
sc_call_rpc(ipc, &msg, false);
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
- RPC_SVC(&msg) = SC_RPC_SVC_TIMER;
- RPC_FUNC(&msg) = TIMER_FUNC_STOP_WDOG;
+ RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_TIMER;
+ RPC_FUNC(&msg) = (uint8_t) TIMER_FUNC_STOP_WDOG;
RPC_SIZE(&msg) = 1;
sc_call_rpc(ipc, &msg, false);
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
- RPC_SVC(&msg) = SC_RPC_SVC_TIMER;
- RPC_FUNC(&msg) = TIMER_FUNC_PING_WDOG;
+ RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_TIMER;
+ RPC_FUNC(&msg) = (uint8_t) TIMER_FUNC_PING_WDOG;
RPC_SIZE(&msg) = 1;
sc_call_rpc(ipc, &msg, false);
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
- RPC_SVC(&msg) = SC_RPC_SVC_TIMER;
- RPC_FUNC(&msg) = TIMER_FUNC_GET_WDOG_STATUS;
+ RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_TIMER;
+ RPC_FUNC(&msg) = (uint8_t) TIMER_FUNC_GET_WDOG_STATUS;
RPC_SIZE(&msg) = 1;
sc_call_rpc(ipc, &msg, false);
if (timeout != NULL)
+ {
*timeout = RPC_U32(&msg, 0);
+ }
+
if (max_timeout != NULL)
+ {
*max_timeout = RPC_U32(&msg, 4);
+ }
+
if (remaining_time != NULL)
+ {
*remaining_time = RPC_U32(&msg, 8);
+ }
+
result = RPC_R8(&msg);
return (sc_err_t) result;
}
+sc_err_t sc_timer_pt_get_wdog_status(sc_ipc_t ipc, sc_rm_pt_t pt, bool *enb,
+ sc_timer_wdog_time_t *timeout, sc_timer_wdog_time_t *remaining_time)
+{
+ sc_rpc_msg_t msg;
+ uint8_t result;
+
+ RPC_VER(&msg) = SC_RPC_VERSION;
+ RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_TIMER;
+ RPC_FUNC(&msg) = (uint8_t) TIMER_FUNC_PT_GET_WDOG_STATUS;
+ RPC_U8(&msg, 0) = pt;
+ RPC_SIZE(&msg) = 2;
+
+ sc_call_rpc(ipc, &msg, false);
+
+ if (timeout != NULL)
+ {
+ *timeout = RPC_U32(&msg, 0);
+ }
+
+ if (remaining_time != NULL)
+ {
+ *remaining_time = RPC_U32(&msg, 4);
+ }
+
+ result = RPC_R8(&msg);
+ if (enb != NULL)
+ {
+ *enb = RPC_U8(&msg, 8);
+ }
+
+ return (sc_err_t) result;
+}
+
sc_err_t sc_timer_set_wdog_action(sc_ipc_t ipc,
sc_rm_pt_t pt, sc_timer_wdog_action_t action)
{
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
- RPC_SVC(&msg) = SC_RPC_SVC_TIMER;
- RPC_FUNC(&msg) = TIMER_FUNC_SET_WDOG_ACTION;
+ RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_TIMER;
+ RPC_FUNC(&msg) = (uint8_t) TIMER_FUNC_SET_WDOG_ACTION;
RPC_U8(&msg, 0) = pt;
RPC_U8(&msg, 1) = action;
RPC_SIZE(&msg) = 2;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
- RPC_SVC(&msg) = SC_RPC_SVC_TIMER;
- RPC_FUNC(&msg) = TIMER_FUNC_SET_RTC_TIME;
+ RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_TIMER;
+ RPC_FUNC(&msg) = (uint8_t) TIMER_FUNC_SET_RTC_TIME;
RPC_U16(&msg, 0) = year;
RPC_U8(&msg, 2) = mon;
RPC_U8(&msg, 3) = day;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
- RPC_SVC(&msg) = SC_RPC_SVC_TIMER;
- RPC_FUNC(&msg) = TIMER_FUNC_GET_RTC_TIME;
+ RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_TIMER;
+ RPC_FUNC(&msg) = (uint8_t) TIMER_FUNC_GET_RTC_TIME;
RPC_SIZE(&msg) = 1;
sc_call_rpc(ipc, &msg, false);
if (year != NULL)
+ {
*year = RPC_U16(&msg, 0);
+ }
+
result = RPC_R8(&msg);
if (mon != NULL)
+ {
*mon = RPC_U8(&msg, 2);
+ }
+
if (day != NULL)
+ {
*day = RPC_U8(&msg, 3);
+ }
+
if (hour != NULL)
+ {
*hour = RPC_U8(&msg, 4);
+ }
+
if (min != NULL)
+ {
*min = RPC_U8(&msg, 5);
+ }
+
if (sec != NULL)
+ {
*sec = RPC_U8(&msg, 6);
+ }
+
return (sc_err_t) result;
}
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
- RPC_SVC(&msg) = SC_RPC_SVC_TIMER;
- RPC_FUNC(&msg) = TIMER_FUNC_GET_RTC_SEC1970;
+ RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_TIMER;
+ RPC_FUNC(&msg) = (uint8_t) TIMER_FUNC_GET_RTC_SEC1970;
RPC_SIZE(&msg) = 1;
sc_call_rpc(ipc, &msg, false);
if (sec != NULL)
+ {
*sec = RPC_U32(&msg, 0);
+ }
+
result = RPC_R8(&msg);
return (sc_err_t) result;
}
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
- RPC_SVC(&msg) = SC_RPC_SVC_TIMER;
- RPC_FUNC(&msg) = TIMER_FUNC_SET_RTC_ALARM;
+ RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_TIMER;
+ RPC_FUNC(&msg) = (uint8_t) TIMER_FUNC_SET_RTC_ALARM;
RPC_U16(&msg, 0) = year;
RPC_U8(&msg, 2) = mon;
RPC_U8(&msg, 3) = day;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
- RPC_SVC(&msg) = SC_RPC_SVC_TIMER;
- RPC_FUNC(&msg) = TIMER_FUNC_SET_RTC_CALB;
+ RPC_SVC(&msg) = (uint8_t) SC_RPC_SVC_TIMER;
+ RPC_FUNC(&msg) = (uint8_t) TIMER_FUNC_SET_RTC_CALB;
RPC_I8(&msg, 0) = count;
RPC_SIZE(&msg) = 2;
/*!
* Header file used to configure SoC pad list.
- *
*/
#ifndef _SC_PADS_H
#define SC_P_GPT1_CLK 18 /*!< LSIO.GPT1.CLK, DMA.I2C2.SCL, LSIO.KPP0.COL7, LSIO.GPIO0.IO17 */
#define SC_P_GPT1_CAPTURE 19 /*!< LSIO.GPT1.CAPTURE, DMA.I2C2.SDA, LSIO.KPP0.ROW4, LSIO.GPIO0.IO18 */
#define SC_P_GPT1_COMPARE 20 /*!< LSIO.GPT1.COMPARE, LSIO.PWM2.OUT, LSIO.KPP0.ROW5, LSIO.GPIO0.IO19 */
-#define SC_P_UART0_RX 21 /*!< DMA.UART0.RX, LSIO.GPIO0.IO20 */
-#define SC_P_UART0_TX 22 /*!< DMA.UART0.TX, LSIO.GPIO0.IO21 */
+#define SC_P_UART0_RX 21 /*!< DMA.UART0.RX, SCU.UART0.RX, LSIO.GPIO0.IO20 */
+#define SC_P_UART0_TX 22 /*!< DMA.UART0.TX, SCU.UART0.TX, LSIO.GPIO0.IO21 */
#define SC_P_UART0_RTS_B 23 /*!< DMA.UART0.RTS_B, LSIO.PWM0.OUT, DMA.UART2.RX, LSIO.GPIO0.IO22 */
#define SC_P_UART0_CTS_B 24 /*!< DMA.UART0.CTS_B, LSIO.PWM1.OUT, DMA.UART2.TX, LSIO.GPIO0.IO23 */
#define SC_P_UART1_TX 25 /*!< DMA.UART1.TX, DMA.SPI3.SCK, LSIO.GPIO0.IO24 */
#define SC_P_MIPI_CSI0_MCLK_OUT 72 /*!< MIPI_CSI0.ACM.MCLK_OUT, LSIO.GPIO1.IO24 */
#define SC_P_MIPI_CSI0_I2C0_SCL 73 /*!< MIPI_CSI0.I2C0.SCL, LSIO.GPIO1.IO25 */
#define SC_P_MIPI_CSI0_I2C0_SDA 74 /*!< MIPI_CSI0.I2C0.SDA, LSIO.GPIO1.IO26 */
-#define SC_P_MIPI_CSI0_GPIO0_00 75 /*!< MIPI_CSI0.GPIO0.IO00, DMA.I2C0.SCL, LSIO.GPIO1.IO27 */
-#define SC_P_MIPI_CSI0_GPIO0_01 76 /*!< MIPI_CSI0.GPIO0.IO01, DMA.I2C0.SDA, LSIO.GPIO1.IO28 */
+#define SC_P_MIPI_CSI0_GPIO0_00 75 /*!< MIPI_CSI0.GPIO0.IO00, DMA.I2C0.SCL, MIPI_CSI1.I2C0.SCL, LSIO.GPIO1.IO27 */
+#define SC_P_MIPI_CSI0_GPIO0_01 76 /*!< MIPI_CSI0.GPIO0.IO01, DMA.I2C0.SDA, MIPI_CSI1.I2C0.SDA, LSIO.GPIO1.IO28 */
#define SC_P_MIPI_CSI1_MCLK_OUT 77 /*!< MIPI_CSI1.ACM.MCLK_OUT, LSIO.GPIO1.IO29 */
#define SC_P_MIPI_CSI1_GPIO0_00 78 /*!< MIPI_CSI1.GPIO0.IO00, DMA.UART4.RX, LSIO.GPIO1.IO30 */
#define SC_P_MIPI_CSI1_GPIO0_01 79 /*!< MIPI_CSI1.GPIO0.IO01, DMA.UART4.TX, LSIO.GPIO1.IO31 */
#define SC_P_HDMI_TX0_TS_SDA 83 /*!< HDMI_TX0.I2C0.SDA, DMA.I2C0.SDA, LSIO.GPIO2.IO03 */
#define SC_P_COMP_CTL_GPIO_3V3_HDMIGPIO 84 /*!< */
#define SC_P_ESAI1_FSR 85 /*!< AUD.ESAI1.FSR, LSIO.GPIO2.IO04 */
-#define SC_P_ESAI1_FST 86 /*!< AUD.ESAI1.FST, LSIO.GPIO2.IO05 */
+#define SC_P_ESAI1_FST 86 /*!< AUD.ESAI1.FST, AUD.SPDIF0.EXT_CLK, LSIO.GPIO2.IO05 */
#define SC_P_ESAI1_SCKR 87 /*!< AUD.ESAI1.SCKR, LSIO.GPIO2.IO06 */
-#define SC_P_ESAI1_SCKT 88 /*!< AUD.ESAI1.SCKT, AUD.SAI2.RXC, LSIO.GPIO2.IO07 */
-#define SC_P_ESAI1_TX0 89 /*!< AUD.ESAI1.TX0, AUD.SAI2.RXD, LSIO.GPIO2.IO08 */
-#define SC_P_ESAI1_TX1 90 /*!< AUD.ESAI1.TX1, AUD.SAI2.RXFS, LSIO.GPIO2.IO09 */
-#define SC_P_ESAI1_TX2_RX3 91 /*!< AUD.ESAI1.TX2_RX3, LSIO.GPIO2.IO10 */
-#define SC_P_ESAI1_TX3_RX2 92 /*!< AUD.ESAI1.TX3_RX2, LSIO.GPIO2.IO11 */
+#define SC_P_ESAI1_SCKT 88 /*!< AUD.ESAI1.SCKT, AUD.SAI2.RXC, AUD.SPDIF0.EXT_CLK, LSIO.GPIO2.IO07 */
+#define SC_P_ESAI1_TX0 89 /*!< AUD.ESAI1.TX0, AUD.SAI2.RXD, AUD.SPDIF0.RX, LSIO.GPIO2.IO08 */
+#define SC_P_ESAI1_TX1 90 /*!< AUD.ESAI1.TX1, AUD.SAI2.RXFS, AUD.SPDIF0.TX, LSIO.GPIO2.IO09 */
+#define SC_P_ESAI1_TX2_RX3 91 /*!< AUD.ESAI1.TX2_RX3, AUD.SPDIF0.RX, LSIO.GPIO2.IO10 */
+#define SC_P_ESAI1_TX3_RX2 92 /*!< AUD.ESAI1.TX3_RX2, AUD.SPDIF0.TX, LSIO.GPIO2.IO11 */
#define SC_P_ESAI1_TX4_RX1 93 /*!< AUD.ESAI1.TX4_RX1, LSIO.GPIO2.IO12 */
#define SC_P_ESAI1_TX5_RX0 94 /*!< AUD.ESAI1.TX5_RX0, LSIO.GPIO2.IO13 */
#define SC_P_SPDIF0_RX 95 /*!< AUD.SPDIF0.RX, AUD.MQS.R, AUD.ACM.MCLK_IN1, LSIO.GPIO2.IO14 */
#define SC_P_ESAI0_TX3_RX2 111 /*!< AUD.ESAI0.TX3_RX2, LSIO.GPIO2.IO29 */
#define SC_P_ESAI0_TX4_RX1 112 /*!< AUD.ESAI0.TX4_RX1, LSIO.GPIO2.IO30 */
#define SC_P_ESAI0_TX5_RX0 113 /*!< AUD.ESAI0.TX5_RX0, LSIO.GPIO2.IO31 */
-#define SC_P_MCLK_IN0 114 /*!< AUD.ACM.MCLK_IN0, AUD.ESAI0.RX_HF_CLK, LSIO.GPIO3.IO00 */
-#define SC_P_MCLK_OUT0 115 /*!< AUD.ACM.MCLK_OUT0, AUD.ESAI0.TX_HF_CLK, LSIO.GPIO3.IO01 */
+#define SC_P_MCLK_IN0 114 /*!< AUD.ACM.MCLK_IN0, AUD.ESAI0.RX_HF_CLK, AUD.ESAI1.RX_HF_CLK, LSIO.GPIO3.IO00 */
+#define SC_P_MCLK_OUT0 115 /*!< AUD.ACM.MCLK_OUT0, AUD.ESAI0.TX_HF_CLK, AUD.ESAI1.TX_HF_CLK, LSIO.GPIO3.IO01 */
#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHC 116 /*!< */
#define SC_P_SPI0_SCK 117 /*!< DMA.SPI0.SCK, AUD.SAI0.RXC, LSIO.GPIO3.IO02 */
#define SC_P_SPI0_SDO 118 /*!< DMA.SPI0.SDO, AUD.SAI0.TXD, LSIO.GPIO3.IO03 */
#define SC_P_QSPI1A_SS1_B 173 /*!< LSIO.QSPI1A.SS1_B, LSIO.QSPI1A.SCLK2, LSIO.GPIO4.IO20 */
#define SC_P_QSPI1A_SCLK 174 /*!< LSIO.QSPI1A.SCLK, LSIO.GPIO4.IO21 */
#define SC_P_QSPI1A_DQS 175 /*!< LSIO.QSPI1A.DQS, LSIO.GPIO4.IO22 */
-#define SC_P_QSPI1A_DATA3 176 /*!< LSIO.QSPI1A.DATA3, LSIO.GPIO4.IO23 */
-#define SC_P_QSPI1A_DATA2 177 /*!< LSIO.QSPI1A.DATA2, LSIO.GPIO4.IO24 */
-#define SC_P_QSPI1A_DATA1 178 /*!< LSIO.QSPI1A.DATA1, LSIO.GPIO4.IO25 */
+#define SC_P_QSPI1A_DATA3 176 /*!< LSIO.QSPI1A.DATA3, DMA.I2C1.SDA, CONN.USB_OTG1.OC, LSIO.GPIO4.IO23 */
+#define SC_P_QSPI1A_DATA2 177 /*!< LSIO.QSPI1A.DATA2, DMA.I2C1.SCL, CONN.USB_OTG2.PWR, LSIO.GPIO4.IO24 */
+#define SC_P_QSPI1A_DATA1 178 /*!< LSIO.QSPI1A.DATA1, DMA.I2C1.SDA, CONN.USB_OTG2.OC, LSIO.GPIO4.IO25 */
#define SC_P_QSPI1A_DATA0 179 /*!< LSIO.QSPI1A.DATA0, LSIO.GPIO4.IO26 */
#define SC_P_COMP_CTL_GPIO_1V8_3V3_QSPI1 180 /*!< */
#define SC_P_QSPI0A_DATA0 181 /*!< LSIO.QSPI0A.DATA0 */
#define SC_P_PCIE_CTRL0_CLKREQ_B 198 /*!< HSIO.PCIE0.CLKREQ_B, LSIO.GPIO4.IO27 */
#define SC_P_PCIE_CTRL0_WAKE_B 199 /*!< HSIO.PCIE0.WAKE_B, LSIO.GPIO4.IO28 */
#define SC_P_PCIE_CTRL0_PERST_B 200 /*!< HSIO.PCIE0.PERST_B, LSIO.GPIO4.IO29 */
-#define SC_P_PCIE_CTRL1_CLKREQ_B 201 /*!< HSIO.PCIE1.CLKREQ_B, LSIO.GPIO4.IO30 */
-#define SC_P_PCIE_CTRL1_WAKE_B 202 /*!< HSIO.PCIE1.WAKE_B, LSIO.GPIO4.IO31 */
-#define SC_P_PCIE_CTRL1_PERST_B 203 /*!< HSIO.PCIE1.PERST_B, LSIO.GPIO5.IO00 */
+#define SC_P_PCIE_CTRL1_CLKREQ_B 201 /*!< HSIO.PCIE1.CLKREQ_B, DMA.I2C1.SDA, CONN.USB_OTG2.OC, LSIO.GPIO4.IO30 */
+#define SC_P_PCIE_CTRL1_WAKE_B 202 /*!< HSIO.PCIE1.WAKE_B, DMA.I2C1.SCL, CONN.USB_OTG2.PWR, LSIO.GPIO4.IO31 */
+#define SC_P_PCIE_CTRL1_PERST_B 203 /*!< HSIO.PCIE1.PERST_B, DMA.I2C1.SCL, CONN.USB_OTG1.PWR, LSIO.GPIO5.IO00 */
#define SC_P_COMP_CTL_GPIO_1V8_3V3_PCIESEP 204 /*!< */
#define SC_P_USB_HSIC0_DATA 205 /*!< CONN.USB_HSIC0.DATA, DMA.I2C1.SDA, LSIO.GPIO5.IO01 */
#define SC_P_USB_HSIC0_STROBE 206 /*!< CONN.USB_HSIC0.STROBE, DMA.I2C1.SCL, LSIO.GPIO5.IO02 */
#define SC_P_CALIBRATION_0_HSIC 207 /*!< */
#define SC_P_CALIBRATION_1_HSIC 208 /*!< */
#define SC_P_EMMC0_CLK 209 /*!< CONN.EMMC0.CLK, CONN.NAND.READY_B */
-#define SC_P_EMMC0_CMD 210 /*!< CONN.EMMC0.CMD, CONN.NAND.DQS, LSIO.GPIO5.IO03 */
+#define SC_P_EMMC0_CMD 210 /*!< CONN.EMMC0.CMD, CONN.NAND.DQS, AUD.MQS.R, LSIO.GPIO5.IO03 */
#define SC_P_EMMC0_DATA0 211 /*!< CONN.EMMC0.DATA0, CONN.NAND.DATA00, LSIO.GPIO5.IO04 */
#define SC_P_EMMC0_DATA1 212 /*!< CONN.EMMC0.DATA1, CONN.NAND.DATA01, LSIO.GPIO5.IO05 */
#define SC_P_EMMC0_DATA2 213 /*!< CONN.EMMC0.DATA2, CONN.NAND.DATA02, LSIO.GPIO5.IO06 */
#define SC_P_EMMC0_DATA6 217 /*!< CONN.EMMC0.DATA6, CONN.NAND.DATA06, LSIO.GPIO5.IO10 */
#define SC_P_EMMC0_DATA7 218 /*!< CONN.EMMC0.DATA7, CONN.NAND.DATA07, LSIO.GPIO5.IO11 */
#define SC_P_EMMC0_STROBE 219 /*!< CONN.EMMC0.STROBE, CONN.NAND.CLE, LSIO.GPIO5.IO12 */
-#define SC_P_EMMC0_RESET_B 220 /*!< CONN.EMMC0.RESET_B, CONN.NAND.WP_B, LSIO.GPIO5.IO13 */
+#define SC_P_EMMC0_RESET_B 220 /*!< CONN.EMMC0.RESET_B, CONN.NAND.WP_B, CONN.USDHC1.VSELECT, LSIO.GPIO5.IO13 */
#define SC_P_COMP_CTL_GPIO_1V8_3V3_SD1FIX 221 /*!< */
-#define SC_P_USDHC1_CLK 222 /*!< CONN.USDHC1.CLK */
-#define SC_P_USDHC1_CMD 223 /*!< CONN.USDHC1.CMD, LSIO.GPIO5.IO14 */
+#define SC_P_USDHC1_CLK 222 /*!< CONN.USDHC1.CLK, AUD.MQS.R */
+#define SC_P_USDHC1_CMD 223 /*!< CONN.USDHC1.CMD, AUD.MQS.L, LSIO.GPIO5.IO14 */
#define SC_P_USDHC1_DATA0 224 /*!< CONN.USDHC1.DATA0, CONN.NAND.RE_N, LSIO.GPIO5.IO15 */
#define SC_P_USDHC1_DATA1 225 /*!< CONN.USDHC1.DATA1, CONN.NAND.RE_P, LSIO.GPIO5.IO16 */
#define SC_P_CTL_NAND_RE_P_N 226 /*!< */
#define SC_P_USDHC1_DATA2 227 /*!< CONN.USDHC1.DATA2, CONN.NAND.DQS_N, LSIO.GPIO5.IO17 */
#define SC_P_USDHC1_DATA3 228 /*!< CONN.USDHC1.DATA3, CONN.NAND.DQS_P, LSIO.GPIO5.IO18 */
#define SC_P_CTL_NAND_DQS_P_N 229 /*!< */
-#define SC_P_USDHC1_DATA4 230 /*!< CONN.USDHC1.DATA4, CONN.NAND.CE0_B, LSIO.GPIO5.IO19 */
-#define SC_P_USDHC1_DATA5 231 /*!< CONN.USDHC1.DATA5, CONN.NAND.RE_B, LSIO.GPIO5.IO20 */
+#define SC_P_USDHC1_DATA4 230 /*!< CONN.USDHC1.DATA4, CONN.NAND.CE0_B, AUD.MQS.R, LSIO.GPIO5.IO19 */
+#define SC_P_USDHC1_DATA5 231 /*!< CONN.USDHC1.DATA5, CONN.NAND.RE_B, AUD.MQS.L, LSIO.GPIO5.IO20 */
#define SC_P_USDHC1_DATA6 232 /*!< CONN.USDHC1.DATA6, CONN.NAND.WE_B, CONN.USDHC1.WP, LSIO.GPIO5.IO21 */
#define SC_P_USDHC1_DATA7 233 /*!< CONN.USDHC1.DATA7, CONN.NAND.ALE, CONN.USDHC1.CD_B, LSIO.GPIO5.IO22 */
-#define SC_P_USDHC1_STROBE 234 /*!< CONN.USDHC1.STROBE, CONN.NAND.CE1_B, LSIO.GPIO5.IO23 */
+#define SC_P_USDHC1_STROBE 234 /*!< CONN.USDHC1.STROBE, CONN.NAND.CE1_B, CONN.USDHC1.RESET_B, LSIO.GPIO5.IO23 */
#define SC_P_COMP_CTL_GPIO_1V8_3V3_VSEL2 235 /*!< */
#define SC_P_USDHC2_CLK 236 /*!< CONN.USDHC2.CLK, AUD.MQS.R, LSIO.GPIO5.IO24 */
#define SC_P_USDHC2_CMD 237 /*!< CONN.USDHC2.CMD, AUD.MQS.L, LSIO.GPIO5.IO25 */
#define SC_P_ENET0_RGMII_TX_CTL 244 /*!< CONN.ENET0.RGMII_TX_CTL, LSIO.GPIO5.IO31 */
#define SC_P_ENET0_RGMII_TXD0 245 /*!< CONN.ENET0.RGMII_TXD0, LSIO.GPIO6.IO00 */
#define SC_P_ENET0_RGMII_TXD1 246 /*!< CONN.ENET0.RGMII_TXD1, LSIO.GPIO6.IO01 */
-#define SC_P_ENET0_RGMII_TXD2 247 /*!< CONN.ENET0.RGMII_TXD2, LSIO.GPIO6.IO02 */
-#define SC_P_ENET0_RGMII_TXD3 248 /*!< CONN.ENET0.RGMII_TXD3, LSIO.GPIO6.IO03 */
-#define SC_P_ENET0_RGMII_RXC 249 /*!< CONN.ENET0.RGMII_RXC, LSIO.GPIO6.IO04 */
-#define SC_P_ENET0_RGMII_RX_CTL 250 /*!< CONN.ENET0.RGMII_RX_CTL, LSIO.GPIO6.IO05 */
-#define SC_P_ENET0_RGMII_RXD0 251 /*!< CONN.ENET0.RGMII_RXD0, LSIO.GPIO6.IO06 */
-#define SC_P_ENET0_RGMII_RXD1 252 /*!< CONN.ENET0.RGMII_RXD1, LSIO.GPIO6.IO07 */
-#define SC_P_ENET0_RGMII_RXD2 253 /*!< CONN.ENET0.RGMII_RXD2, CONN.ENET0.RMII_RX_ER, LSIO.GPIO6.IO08 */
-#define SC_P_ENET0_RGMII_RXD3 254 /*!< CONN.ENET0.RGMII_RXD3, LSIO.GPIO6.IO09 */
+#define SC_P_ENET0_RGMII_TXD2 247 /*!< CONN.ENET0.RGMII_TXD2, DMA.UART3.TX, VPU.TSI_S1.VID, LSIO.GPIO6.IO02 */
+#define SC_P_ENET0_RGMII_TXD3 248 /*!< CONN.ENET0.RGMII_TXD3, DMA.UART3.RTS_B, VPU.TSI_S1.SYNC, LSIO.GPIO6.IO03 */
+#define SC_P_ENET0_RGMII_RXC 249 /*!< CONN.ENET0.RGMII_RXC, DMA.UART3.CTS_B, VPU.TSI_S1.DATA, LSIO.GPIO6.IO04 */
+#define SC_P_ENET0_RGMII_RX_CTL 250 /*!< CONN.ENET0.RGMII_RX_CTL, VPU.TSI_S0.VID, LSIO.GPIO6.IO05 */
+#define SC_P_ENET0_RGMII_RXD0 251 /*!< CONN.ENET0.RGMII_RXD0, VPU.TSI_S0.SYNC, LSIO.GPIO6.IO06 */
+#define SC_P_ENET0_RGMII_RXD1 252 /*!< CONN.ENET0.RGMII_RXD1, VPU.TSI_S0.DATA, LSIO.GPIO6.IO07 */
+#define SC_P_ENET0_RGMII_RXD2 253 /*!< CONN.ENET0.RGMII_RXD2, CONN.ENET0.RMII_RX_ER, VPU.TSI_S0.CLK, LSIO.GPIO6.IO08 */
+#define SC_P_ENET0_RGMII_RXD3 254 /*!< CONN.ENET0.RGMII_RXD3, DMA.UART3.RX, VPU.TSI_S1.CLK, LSIO.GPIO6.IO09 */
#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB 255 /*!< */
#define SC_P_ENET1_RGMII_TXC 256 /*!< CONN.ENET1.RGMII_TXC, CONN.ENET1.RCLK50M_OUT, CONN.ENET1.RCLK50M_IN, LSIO.GPIO6.IO10 */
#define SC_P_ENET1_RGMII_TX_CTL 257 /*!< CONN.ENET1.RGMII_TX_CTL, LSIO.GPIO6.IO11 */
/*!
* Header file used to configure SoC pad list.
- *
*/
#ifndef _SC_PADS_H
#define SC_P_FLEXCAN1_TX 108 /*!< ADMA.FLEXCAN1.TX, ADMA.SAI3.RXC, ADMA.DMA0.REQ_IN0, ADMA.SAI1.RXD, LSIO.GPIO1.IO18 */
#define SC_P_FLEXCAN2_RX 109 /*!< ADMA.FLEXCAN2.RX, ADMA.SAI3.RXD, ADMA.UART3.RX, ADMA.SAI1.RXFS, LSIO.GPIO1.IO19 */
#define SC_P_FLEXCAN2_TX 110 /*!< ADMA.FLEXCAN2.TX, ADMA.SAI3.RXFS, ADMA.UART3.TX, ADMA.SAI1.RXC, LSIO.GPIO1.IO20 */
-#define SC_P_UART0_RX 111 /*!< ADMA.UART0.RX, ADMA.MQS.R, ADMA.FLEXCAN0.RX, LSIO.GPIO1.IO21 */
-#define SC_P_UART0_TX 112 /*!< ADMA.UART0.TX, ADMA.MQS.L, ADMA.FLEXCAN0.TX, LSIO.GPIO1.IO22 */
+#define SC_P_UART0_RX 111 /*!< ADMA.UART0.RX, ADMA.MQS.R, ADMA.FLEXCAN0.RX, SCU.UART0.RX, LSIO.GPIO1.IO21 */
+#define SC_P_UART0_TX 112 /*!< ADMA.UART0.TX, ADMA.MQS.L, ADMA.FLEXCAN0.TX, SCU.UART0.TX, LSIO.GPIO1.IO22 */
#define SC_P_UART2_TX 113 /*!< ADMA.UART2.TX, ADMA.FTM.CH1, ADMA.FLEXCAN1.TX, LSIO.GPIO1.IO23 */
#define SC_P_UART2_RX 114 /*!< ADMA.UART2.RX, ADMA.FTM.CH0, ADMA.FLEXCAN1.RX, LSIO.GPIO1.IO24 */
#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOLH 115 /*!< */
#define RPC_SVC(MSG) ((MSG)->svc)
#define RPC_FUNC(MSG) ((MSG)->func)
#define RPC_R8(MSG) ((MSG)->func)
-#define RPC_I32(MSG, IDX) ((MSG)->DATA.i32[IDX / 4])
-#define RPC_I16(MSG, IDX) ((MSG)->DATA.i16[IDX / 2])
-#define RPC_I8(MSG, IDX) ((MSG)->DATA.i8[IDX])
-#define RPC_U32(MSG, IDX) ((MSG)->DATA.u32[IDX / 4])
-#define RPC_U16(MSG, IDX) ((MSG)->DATA.u16[IDX / 2])
-#define RPC_U8(MSG, IDX) ((MSG)->DATA.u8[IDX])
+#define RPC_I32(MSG, IDX) ((MSG)->DATA.i32[(IDX) / 4])
+#define RPC_I16(MSG, IDX) ((MSG)->DATA.i16[(IDX) / 2])
+#define RPC_I8(MSG, IDX) ((MSG)->DATA.i8[(IDX)])
+#define RPC_U32(MSG, IDX) ((MSG)->DATA.u32[(IDX) / 4])
+#define RPC_U16(MSG, IDX) ((MSG)->DATA.u16[(IDX) / 2])
+#define RPC_U8(MSG, IDX) ((MSG)->DATA.u8[(IDX)])
/* Types */
/*! Max DMA channel priority group */
#define SC_MISC_DMA_GRP_MAX 31
-
/*!
* @name Defines for sc_misc_boot_status_t
*/
#define SC_MISC_TEMP_LOW 2 /*!< Temp low alarm */
/*@}*/
+/*!
+ * @name Defines for sc_misc_seco_auth_cmd_t
+ */
+/*@{*/
+#define SC_MISC_AUTH_CONTAINER 0 /*!< Authenticate container */
+#define SC_MISC_VERIFY_IMAGE 1 /*!< Verify image */
+#define SC_MISC_REL_CONTAINER 2 /*!< Release container */
+/*@}*/
+
/* Types */
/*!
*
* @param[in] ipc IPC handle
* @param[in] cmd authenticate command
- * @param[in] addr_meta address of metadata
+ * @param[in] addr_meta address of/or metadata
*
* @return Returns an error code (SC_ERR_NONE = success).
*
* This is used to authenticate a SECO image or issue a security
- * command. \a addr_meta often points to an IVT in SECO TCM.
+ * command. \a addr_meta often points to an container. It is also
+ * just data (or even unused) for some commands.
*/
sc_err_t sc_misc_seco_authenticate(sc_ipc_t ipc,
sc_misc_seco_auth_cmd_t cmd, uint32_t addr_meta);
void sc_misc_build_info(sc_ipc_t ipc, uint32_t *build,
uint32_t *commit);
+/*!
+ * This function is used to return the device's unique ID.
+ *
+ * @param[in] ipc IPC handle
+ * @param[out] id_l pointer to return lower 32-bit of ID [31:0]
+ * @param[out] id_h pointer to return upper 32-bits of ID [63:32]
+ */
+void sc_misc_unique_id(sc_ipc_t ipc, uint32_t *id_l,
+ uint32_t *id_h);
+
/* @} */
/*!
*
* Return errors codes:
* - SC_ERR_PARM if word fuse index param out of range or invalid
- * - SC_ERR_NOACCESS if read operation fail
+ * - SC_ERR_NOACCESS if read operation failed
* - SC_ERR_LOCKED if read operation is locked
*/
sc_err_t sc_misc_otp_fuse_read(sc_ipc_t ipc, uint32_t word, uint32_t *val);
+/*!
+ * This function writes a given fuse word index.
+ *
+ * @param[in] ipc IPC handle
+ * @param[in] word fuse word index
+ * @param[in] val fuse write value
+ *
+ * @return Returns and error code (SC_ERR_NONE = success).
+ *
+ * Return errors codes:
+ * - SC_ERR_PARM if word fuse index param out of range or invalid
+ * - SC_ERR_NOACCESS if write operation failed
+ * - SC_ERR_LOCKED if write operation is locked
+ */
+sc_err_t sc_misc_otp_fuse_write(sc_ipc_t ipc, uint32_t word, uint32_t val);
+
/*!
* This function sets a temp sensor alarm.
*
*/
void sc_misc_get_boot_dev(sc_ipc_t ipc, sc_rsrc_t *dev);
+/*!
+ * This function returns the current status of the ON/OFF button.
+ *
+ * @param[in] ipc IPC handle
+ * @param[out] status pointer to return button status
+ */
+void sc_misc_get_button_status(sc_ipc_t ipc, bool *status);
+
/* @} */
#endif /* _SC_MISC_API_H */
#define SC_PM_RESET_REASON_LOW_VOLT 7 /*!< Low voltage reset */
/*@}*/
+/*!
+ * @name Defines for sc_pm_sys_if_t
+ */
+/*@{*/
+#define SC_PM_SYS_IF_INTERCONNECT 0 /*!< System interconnect */
+#define SC_PM_SYS_IF_MU 1 /*!< AP -> SCU message units */
+#define SC_PM_SYS_IF_OCMEM 2 /*!< On-chip memory (ROM/OCRAM) */
+#define SC_PM_SYS_IF_DDR 3 /*!< DDR memory */
+/*@}*/
+
/* Types */
/*!
*/
typedef uint8_t sc_pm_reset_reason_t;
+/*!
+ * This type is used to specify a system-level interface to be power managed.
+ */
+typedef uint8_t sc_pm_sys_if_t;
+
/* Functions */
/*!
* @{
*/
+/*!
+ * This function sets the system power mode. Only the owner of the
+ * SC_R_SYSTEM resource can do this.
+ *
+ * @param[in] ipc IPC handle
+ * @param[in] mode power mode to apply
+ *
+ * @return Returns an error code (SC_ERR_NONE = success).
+ *
+ * Return errors:
+ * - SC_ERR_PARM if invalid mode,
+ * - SC_ERR_NOACCESS if caller not the owner of SC_R_SYSTEM
+ *
+ * @see sc_pm_set_sys_power_mode().
+ */
+sc_err_t sc_pm_set_sys_power_mode(sc_ipc_t ipc, sc_pm_power_mode_t mode);
+
/*!
* This function sets the power mode of a partition.
*
*
* @see sc_pm_set_resource_power_mode().
*/
-sc_err_t sc_pm_set_sys_power_mode(sc_ipc_t ipc, sc_rm_pt_t pt,
+sc_err_t sc_pm_set_partition_power_mode(sc_ipc_t ipc, sc_rm_pt_t pt,
sc_pm_power_mode_t mode);
/*!
* - SC_ERR_NOACCESS if caller's partition is not the resource owner
* or parent of the owner
*
- * Note only SC_PM_PW_MODE_OFF and SC_PM_PW_MODE_ON are valid. Other modes
- * will return an error. Resources set to SC_PM_PW_MODE_ON will reflect the
+ * Resources set to SC_PM_PW_MODE_ON will reflect the
* power mode of the partition and will change as that changes.
*
* Note some resources are still not accessible even when powered up if bus
* resources in display and capture subsystems which require the display
* controller or the imaging subsytem to be powered up first.
*
- * @see sc_pm_set_sys_power_mode().
+ * @see sc_pm_set_partition_power_mode().
*/
sc_err_t sc_pm_set_resource_power_mode(sc_ipc_t ipc, sc_rsrc_t resource,
sc_pm_power_mode_t mode);
sc_err_t sc_pm_get_resource_power_mode(sc_ipc_t ipc, sc_rsrc_t resource,
sc_pm_power_mode_t *mode);
+/*!
+ * This function requests the low power mode some of the resources
+ * can enter based on their state. This API is only valid for the
+ * following resources : SC_R_A53, SC_R_A53_0, SC_R_A53_1, SC_A53_2,
+ * SC_A53_3, SC_R_A72, SC_R_A72_0, SC_R_A72_1, SC_R_CC1, SC_R_A35,
+ * SC_R_A35_0, SC_R_A35_1, SC_R_A35_2, SC_R_A35_3.
+ * For all other resources it will return SC_ERR_PARAM.
+ * This function will set the low power mode the cores, cluster
+ * and cluster associated resources will enter when all the cores
+ * in a given cluster execute WFI
+ *
+ * @param[in] ipc IPC handle
+ * @param[in] resource ID of the resource
+ * @param[out] mode pointer to return power mode
+ *
+ * @return Returns an error code (SC_ERR_NONE = success).
+ *
+ */
+sc_err_t sc_pm_req_low_power_mode(sc_ipc_t ipc, sc_rsrc_t resource,
+ sc_pm_power_mode_t mode);
+
+/*!
+ * This function is used to set the resume address of a CPU.
+ *
+ * @param[in] ipc IPC handle
+ * @param[in] resource ID of the CPU resource
+ * @param[in] address 64-bit resume address
+ *
+ * @return Returns an error code (SC_ERR_NONE = success).
+ *
+ * Return errors:
+ * - SC_ERR_PARM if invalid resource or address,
+ * - SC_ERR_NOACCESS if caller's partition is not the parent of the
+ * resource (CPU) owner
+ */
+sc_err_t sc_pm_set_cpu_resume_addr(sc_ipc_t ipc, sc_rsrc_t resource,
+ sc_faddr_t address);
+
+/*!
+ * This function requests the power mode configuration for system-level
+ * interfaces including messaging units, interconnect, and memories. This API
+ * is only valid for the following resources : SC_R_A53, SC_R_A72, and
+ * SC_R_M4_x_PID_y. For all other resources, it will return SC_ERR_PARAM.
+ * The requested power mode will be captured and applied to system-level
+ * resources as system conditions allow.
+ *
+ * @param[in] ipc IPC handle
+ * @param[in] resource ID of the resource
+ * @param[in] sys_if system-level interface to be configured
+ * @param[in] hpm high-power mode for the system interface
+ * @param[in] lpm low-power mode for the system interface
+ *
+ * @return Returns an error code (SC_ERR_NONE = success).
+ *
+ */
+sc_err_t sc_pm_req_sys_if_power_mode(sc_ipc_t ipc, sc_rsrc_t resource,
+ sc_pm_sys_if_t sys_if, sc_pm_power_mode_t hpm, sc_pm_power_mode_t lpm);
+
/* @} */
/*!
sc_err_t sc_pm_clock_enable(sc_ipc_t ipc, sc_rsrc_t resource,
sc_pm_clk_t clk, bool enable, bool autog);
-
/*!
* This function sets the parent of a resource's clock.
* This function should only be called when the clock is disabled.
* @return Returns an error code (SC_ERR_NONE = success).
*
* Return errors:
- * - SC_ERR_PARM if invalid type
+ * - SC_ERR_PARM if invalid type,
+ * - SC_ERR_NOACCESS if caller not the owner of SC_R_SYSTEM
*
* If this function returns, then the reset did not occur due to an
* invalid parameter.
*
* Module for the Resource Management (RM) service.
*
+ * @includedoc rm/details.dox
+ *
* @{
*/
* via XRDC; set true if new DID is desired
* @param[in] restricted boolean indicating if this partition should be restricted; set
* true if masters in this partition cannot create new partitions
- * @param[in] confidential boolean indicating if this partition should be confidential;
- * set true if only this partition should be able to grant
- * resource access permissions to this partition
+ * @param[in] grant boolean indicating if this partition should always grant
+ * access and control to the parent
* @param[in] coherent boolean indicating if this partition is coherent;
* set true if only this partition will contain both AP clusters
* and they will be coherent via the CCI
* Marking as non-secure prevents subsequent functions from configuring masters in this
* partition to assert the secure signal. If restricted then the new partition is limited
* in what functions it can call, especially those associated with managing partitions.
+ *
+ * The grant option is usually used to isolate a bus master's traffic to specific
+ * memory without isolating the peripheral interface of the master or the API
+ * controls of that master.
*/
sc_err_t sc_rm_partition_alloc(sc_ipc_t ipc, sc_rm_pt_t *pt, bool secure,
- bool isolated, bool restricted, bool confidential, bool coherent);
+ bool isolated, bool restricted, bool grant, bool coherent);
+
+/*!
+ * This function makes a partition confidential.
+ *
+ * @param[in] ipc IPC handle
+ * @param[in] pt handle of partition that is granting
+ * @param[in] retro retroactive
+ *
+ * @return Returns an error code (SC_ERR_NONE = success).
+ *
+ * Return errors:
+ * - SC_PARM if \a pt out of range,
+ * - SC_ERR_NOACCESS if caller's not allowed to change \a pt
+ * - SC_ERR_LOCKED if partition \a pt is locked
+ *
+ * Call to make a partition confidential. Confidential means only this
+ * partition should be able to grant access permissions to this partition.
+ *
+ * If retroactive, then all resources owned by other partitions will have
+ * access rights for this partition removed, even if locked.
+ */
+sc_err_t sc_rm_set_confidential(sc_ipc_t ipc, sc_rm_pt_t pt, bool retro);
/*!
* This function frees a partition and assigns all resources to the caller.
* - SC_ERR_NOACCESS if caller's partition is not the region owner or parent
* of the owner,
* - SC_ERR_LOCKED if the owning partition is locked
+ * - SC_ERR_LOCKED if the \a pt is confidential and the caller isn't \a pt
*
* This function configures how the HW isolation will restrict access to a
* memory region based on the attributes of a transaction from bus master.
* @name Defines for type widths
*/
/*@{*/
-#define SC_TIMER_ACTION_W 2 /*!< Width of sc_timer_wdog_action_t */
+#define SC_TIMER_ACTION_W 3 /*!< Width of sc_timer_wdog_action_t */
/*@}*/
/*!
#define SC_TIMER_WDOG_ACTION_WARM 1 /*!< Warm reset system */
#define SC_TIMER_WDOG_ACTION_COLD 2 /*!< Cold reset system */
#define SC_TIMER_WDOG_ACTION_BOARD 3 /*!< Reset board */
+#define SC_TIMER_WDOG_ACTION_IRQ 4 /*!< Only generate IRQs */
/*@}*/
/* Types */
sc_err_t sc_timer_set_wdog_timeout(sc_ipc_t ipc,
sc_timer_wdog_time_t timeout);
+/*!
+ * This function sets the watchdog pre-timeout in milliseconds. If not
+ * set then the pre-timeout defaults to the max. Once locked this value
+ * cannot be changed.
+ *
+ * @param[in] ipc IPC handle
+ * @param[in] pre_timeout pre-timeout period for the watchdog
+ *
+ * When the pre-timout expires an IRQ will be generated. Note this timeout
+ * clears when the IRQ is triggered. An IRQ is generated for the failing
+ * partition and all of its child partitions.
+ *
+ * @return Returns an error code (SC_ERR_NONE = success).
+ */
+sc_err_t sc_timer_set_wdog_pre_timeout(sc_ipc_t ipc,
+ sc_timer_wdog_time_t pre_timeout);
+
/*!
* This function starts the watchdog.
*
* This function gets the status of the watchdog. All arguments are
* in milliseconds.
*
- * @param[in] ipc IPC handle
+ * @param[in] ipc IPC handle
* @param[out] timeout pointer to return the timeout
* @param[out] max_timeout pointer to return the max timeout
* @param[out] remaining_time pointer to return the time remaining
sc_timer_wdog_time_t *timeout, sc_timer_wdog_time_t *max_timeout,
sc_timer_wdog_time_t *remaining_time);
+/*!
+ * This function gets the status of the watchdog of a partition. All
+ * arguments are in milliseconds.
+ *
+ * @param[in] ipc IPC handle
+ * @param[in] pt partition to query
+ * @param[out] enb pointer to return enable status
+ * @param[out] timeout pointer to return the timeout
+ * @param[out] remaining_time pointer to return the time remaining
+ * until trigger
+ *
+ * @return Returns an error code (SC_ERR_NONE = success).
+ */
+sc_err_t sc_timer_pt_get_wdog_status(sc_ipc_t ipc, sc_rm_pt_t pt, bool *enb,
+ sc_timer_wdog_time_t *timeout, sc_timer_wdog_time_t *remaining_time);
+
/*!
* This function configures the action to be taken when a watchdog
* expires.
* @param[in] pt partition to affect
* @param[in] action action to take
*
+ * Default action is inherited from the parent.
+ *
* @return Returns an error code (SC_ERR_NONE = success).
*
* Return errors:
* - SC_ERR_PARM if invalid parameters,
* - SC_ERR_NOACCESS if caller's partition is not the SYSTEM owner,
- * - SC_ERR_NOACCESS if caller's partition is not the parent of \a pt,
* - SC_ERR_LOCKED if the watchdog is locked
*/
sc_err_t sc_timer_set_wdog_action(sc_ipc_t ipc,
sc_err_t sc_timer_get_rtc_sec1970(sc_ipc_t ipc, uint32_t *sec);
/*!
- * This function sets the RTC alarm. Only the owner of the SC_R_SYSTEM
- * resource can set the alarm.
+ * This function sets the RTC alarm.
*
* @param[in] ipc IPC handle
* @param[in] year year (min 1970)
* @param[in] min minute (0-59)
* @param[in] sec second (0-59)
*
+ * Note this alarm setting clears when the alarm is triggered.
+ *
* @return Returns an error code (SC_ERR_NONE = success).
*
* Return errors:
#define SC_325MHZ 325000000 /*!< 325MHz */
#define SC_333MHZ 333333333 /*!< 333MHz */
#define SC_350MHZ 350000000 /*!< 350MHz */
+#define SC_372MHZ 372000000 /*!< 372MHz */
#define SC_375MHZ 375000000 /*!< 375MHz */
#define SC_400MHZ 400000000 /*!< 400MHz */
#define SC_500MHZ 500000000 /*!< 500MHz */
#define SC_12MHZ 12000000 /*!< 12MHz */
#define SC_19MHZ 19800000 /*!< 19.8MHz */
#define SC_24MHZ 24000000 /*!< 24MHz */
+#define SC_48MHZ 48000000 /*!< 48MHz */
#define SC_120MHZ 120000000 /*!< 120MHz */
#define SC_132MHZ 132000000 /*!< 132MHz */
#define SC_144MHZ 144000000 /*!< 144MHz */
#define SC_360MHZ 360000000 /*!< 360MHz */
#define SC_384MHZ 384000000 /*!< 384MHz */
#define SC_396MHZ 396000000 /*!< 396MHz */
+#define SC_432MHZ 432000000 /*!< 432MHz */
#define SC_480MHZ 480000000 /*!< 480MHz */
#define SC_600MHZ 600000000 /*!< 600MHz */
#define SC_744MHZ 744000000 /*!< 744MHz */
SC_R_DMA_1_CH29 = 137,
SC_R_DMA_1_CH30 = 138,
SC_R_DMA_1_CH31 = 139,
- SC_R_DRC_0_V = 140,
- SC_R_DRC_0_H = 141,
- SC_R_DRC_1_V = 142,
- SC_R_DRC_1_H = 143,
+ SC_R_UNUSED1 = 140,
+ SC_R_UNUSED2 = 141,
+ SC_R_UNUSED3 = 142,
+ SC_R_UNUSED4 = 143,
SC_R_GPU_0_PID0 = 144,
SC_R_GPU_0_PID1 = 145,
SC_R_GPU_0_PID2 = 146,
SC_R_SAI_0 = 318,
SC_R_SAI_1 = 319,
SC_R_SAI_2 = 320,
- SC_R_SPBA = 321,
- SC_R_QSPI_0 = 322,
- SC_R_SDMA = 323,
- SC_R_IRQSTR_MW = 324,
+ SC_R_IRQSTR_SCU2 = 321,
+ SC_R_IRQSTR_DSP = 322,
+ SC_R_UNUSED5 = 323,
+ SC_R_UNUSED6 = 324,
SC_R_AUDIO_PLL_0 = 325,
SC_R_PI_0 = 326,
SC_R_PI_0_PWM_0 = 327,
SC_R_A35_1 = 509,
SC_R_A35_2 = 510,
SC_R_A35_3 = 511,
- SC_R_HIFI = 512,
- SC_R_HIFI_RAM = 513,
+ SC_R_DSP = 512,
+ SC_R_DSP_RAM = 513,
SC_R_CAAM_JR1_OUT = 514,
SC_R_CAAM_JR2_OUT = 515,
SC_R_CAAM_JR3_OUT = 516,
- SC_R_VPU_DEC = 517,
- SC_R_VPU_ENC = 518,
+ SC_R_VPU_DEC_0 = 517,
+ SC_R_VPU_ENC_0 = 518,
SC_R_CAAM_JR0 = 519,
SC_R_CAAM_JR0_OUT = 520,
SC_R_PMIC_2 = 521,
SC_R_BOARD_R7 = 531,
SC_R_MJPEG_DEC_MP = 532,
SC_R_MJPEG_ENC_MP = 533,
+ SC_R_VPU_TS_0 = 534,
+ SC_R_VPU_MU_0 = 535,
+ SC_R_VPU_MU_1 = 536,
+ SC_R_VPU_MU_2 = 537,
+ SC_R_VPU_MU_3 = 538,
+ SC_R_VPU_ENC_1 = 539,
+ SC_R_VPU = 540,
SC_R_LAST
} sc_rsrc_t;
+/* NOTE - please add by replacing some of the UNUSED from above! */
+
/*!
* This type is used to indicate a control.
*/
projects / u-boot.git / commitdiff