arm64: dts: imx: add imx8qxp mek support

i.MX 8QuadXPlus is a quad (4x) Cortex-A35 proccessor with powerful
graphic and multimedia features. This patch adds imx8qxp mek board
support.

Cc: Mark Rutland <mark.rutland@arm.com>
Cc: devicetree@vger.kernel.org
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Sascha Hauer <kernel@pengutronix.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
index f9be242..0db6e37 100644 (file)
--- a/arch/arm64/boot/dts/freescale/Makefile
+++ b/arch/arm64/boot/dts/freescale/Makefile
@@ -20,3 +20,4 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-qds.dtb
 dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-rdb.dtb
 
 dtb-$(CONFIG_ARCH_MXC) += imx8mq-evk.dtb
+dtb-$(CONFIG_ARCH_MXC) += imx8qxp-mek.dtb

diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
new file mode 100644 (file)
index 0000000..03aad66
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
@@ -0,0 +1,137 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2017~2018 NXP
+ */
+
+/dts-v1/;
+
+#include "imx8qxp.dtsi"
+
+/ {
+       model = "Freescale i.MX8QXP MEK";
+       compatible = "fsl,imx8qxp-mek", "fsl,imx8qxp";
+
+       chosen {
+               stdout-path = &adma_lpuart0;
+       };
+
+       memory@80000000 {
+               device_type = "memory";
+               reg = <0x00000000 0x80000000 0 0x40000000>;
+       };
+
+       reg_usdhc2_vmmc: usdhc2-vmmc {
+               compatible = "regulator-fixed";
+               regulator-name = "SD1_SPWR";
+               regulator-min-microvolt = <3000000>;
+               regulator-max-microvolt = <3000000>;
+               gpio = <&lsio_gpio4 19 GPIO_ACTIVE_HIGH>;
+               enable-active-high;
+       };
+};
+
+&adma_lpuart0 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_lpuart0>;
+       status = "okay";
+};
+
+&fec1 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_fec1>;
+       phy-mode = "rgmii-id";
+       phy-handle = <&ethphy0>;
+       fsl,magic-packet;
+       status = "okay";
+
+       mdio {
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               ethphy0: ethernet-phy@0 {
+                       compatible = "ethernet-phy-ieee802.3-c22";
+                       reg = <0>;
+               };
+
+               ethphy1: ethernet-phy@1 {
+                       compatible = "ethernet-phy-ieee802.3-c22";
+                       reg = <1>;
+               };
+       };
+};
+
+&usdhc1 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_usdhc1>;
+       bus-width = <8>;
+       no-sd;
+       no-sdio;
+       non-removable;
+       status = "okay";
+};
+
+&usdhc2 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_usdhc2>;
+       bus-width = <4>;
+       vmmc-supply = <&reg_usdhc2_vmmc>;
+       cd-gpios = <&lsio_gpio4 22 GPIO_ACTIVE_LOW>;
+       wp-gpios = <&lsio_gpio4 21 GPIO_ACTIVE_HIGH>;
+       status = "okay";
+};
+
+&iomuxc {
+       pinctrl_fec1: fec1grp {
+               fsl,pins = <
+                       IMX8QXP_ENET0_MDC_CONN_ENET0_MDC                        0x06000020
+                       IMX8QXP_ENET0_MDIO_CONN_ENET0_MDIO                      0x06000020
+                       IMX8QXP_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL      0x06000020
+                       IMX8QXP_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC            0x06000020
+                       IMX8QXP_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0          0x06000020
+                       IMX8QXP_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1          0x06000020
+                       IMX8QXP_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2          0x06000020
+                       IMX8QXP_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3          0x06000020
+                       IMX8QXP_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC            0x06000020
+                       IMX8QXP_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL      0x06000020
+                       IMX8QXP_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0          0x06000020
+                       IMX8QXP_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1          0x06000020
+                       IMX8QXP_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2          0x06000020
+                       IMX8QXP_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3          0x06000020
+               >;
+       };
+
+       pinctrl_lpuart0: lpuart0grp {
+               fsl,pins = <
+                       IMX8QXP_UART0_RX_ADMA_UART0_RX                          0x06000020
+                       IMX8QXP_UART0_TX_ADMA_UART0_TX                          0x06000020
+               >;
+       };
+
+       pinctrl_usdhc1: usdhc1grp {
+               fsl,pins = <
+                       IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK                        0x06000041
+                       IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD                        0x00000021
+                       IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0                    0x00000021
+                       IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1                    0x00000021
+                       IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2                    0x00000021
+                       IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3                    0x00000021
+                       IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4                    0x00000021
+                       IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5                    0x00000021
+                       IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6                    0x00000021
+                       IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7                    0x00000021
+                       IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE                  0x00000041
+               >;
+       };
+
+       pinctrl_usdhc2: usdhc2grp {
+               fsl,pins = <
+                       IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK                      0x06000041
+                       IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD                      0x00000021
+                       IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0                  0x00000021
+                       IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1                  0x00000021
+                       IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2                  0x00000021
+                       IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3                  0x00000021
+                       IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT              0x00000021
+               >;
+       };
+};