drm/amdkfd: Make get_tile_config() generic
authorYong Zhao <Yong.Zhao@amd.com>
Wed, 26 Feb 2020 17:49:03 +0000 (12:49 -0500)
committerAlex Deucher <alexander.deucher@amd.com>
Fri, 28 Feb 2020 21:59:20 +0000 (16:59 -0500)
Given we can query all the asic specific information from amdgpu_gfx_config,
we can make get_tile_config() generic.

Signed-off-by: Yong Zhao <Yong.Zhao@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
drivers/gpu/drm/amd/include/kgd_kfd_interface.h

index b0ad3be..13feb31 100644 (file)
@@ -242,6 +242,9 @@ int amdgpu_amdkfd_gpuvm_import_dmabuf(struct kgd_dev *kgd,
 void amdgpu_amdkfd_gpuvm_init_mem_limits(void);
 void amdgpu_amdkfd_unreserve_memory_limit(struct amdgpu_bo *bo);
 
+int amdgpu_amdkfd_get_tile_config(struct kgd_dev *kgd,
+                               struct tile_config *config);
+
 /* KGD2KFD callbacks */
 int kgd2kfd_init(void);
 void kgd2kfd_exit(void);
index 4bcc175..d6549e5 100644 (file)
@@ -319,7 +319,6 @@ const struct kfd2kgd_calls arcturus_kfd2kgd = {
        .address_watch_get_offset = kgd_gfx_v9_address_watch_get_offset,
        .get_atc_vmid_pasid_mapping_info =
                        kgd_gfx_v9_get_atc_vmid_pasid_mapping_info,
-       .get_tile_config = kgd_gfx_v9_get_tile_config,
        .set_vm_context_page_table_base = kgd_set_vm_context_page_table_base,
        .get_hive_id = amdgpu_amdkfd_get_hive_id,
 };
index ca91fff..4ec6d0c 100644 (file)
@@ -42,38 +42,6 @@ enum hqd_dequeue_request_type {
        SAVE_WAVES
 };
 
-/* Because of REG_GET_FIELD() being used, we put this function in the
- * asic specific file.
- */
-static int amdgpu_amdkfd_get_tile_config(struct kgd_dev *kgd,
-               struct tile_config *config)
-{
-       struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
-
-       config->gb_addr_config = adev->gfx.config.gb_addr_config;
-#if 0
-/* TODO - confirm REG_GET_FIELD x2, should be OK as is... but
- * MC_ARB_RAMCFG register doesn't exist on Vega10 - initial amdgpu
- * changes commented out related code, doing the same here for now but
- * need to sync with Ken et al
- */
-       config->num_banks = REG_GET_FIELD(adev->gfx.config.mc_arb_ramcfg,
-                               MC_ARB_RAMCFG, NOOFBANK);
-       config->num_ranks = REG_GET_FIELD(adev->gfx.config.mc_arb_ramcfg,
-                               MC_ARB_RAMCFG, NOOFRANKS);
-#endif
-
-       config->tile_config_ptr = adev->gfx.config.tile_mode_array;
-       config->num_tile_configs =
-                       ARRAY_SIZE(adev->gfx.config.tile_mode_array);
-       config->macro_tile_config_ptr =
-                       adev->gfx.config.macrotile_mode_array;
-       config->num_macro_tile_configs =
-                       ARRAY_SIZE(adev->gfx.config.macrotile_mode_array);
-
-       return 0;
-}
-
 static inline struct amdgpu_device *get_amdgpu_device(struct kgd_dev *kgd)
 {
        return (struct amdgpu_device *)kgd;
@@ -805,7 +773,6 @@ const struct kfd2kgd_calls gfx_v10_kfd2kgd = {
        .address_watch_get_offset = kgd_address_watch_get_offset,
        .get_atc_vmid_pasid_mapping_info =
                        get_atc_vmid_pasid_mapping_info,
-       .get_tile_config = amdgpu_amdkfd_get_tile_config,
        .set_vm_context_page_table_base = set_vm_context_page_table_base,
        .get_hive_id = amdgpu_amdkfd_get_hive_id,
        .get_unique_id = amdgpu_amdkfd_get_unique_id,
index 8f052e9..0b7e787 100644 (file)
@@ -84,31 +84,6 @@ union TCP_WATCH_CNTL_BITS {
        float f32All;
 };
 
-/* Because of REG_GET_FIELD() being used, we put this function in the
- * asic specific file.
- */
-static int get_tile_config(struct kgd_dev *kgd,
-               struct tile_config *config)
-{
-       struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
-
-       config->gb_addr_config = adev->gfx.config.gb_addr_config;
-       config->num_banks = REG_GET_FIELD(adev->gfx.config.mc_arb_ramcfg,
-                               MC_ARB_RAMCFG, NOOFBANK);
-       config->num_ranks = REG_GET_FIELD(adev->gfx.config.mc_arb_ramcfg,
-                               MC_ARB_RAMCFG, NOOFRANKS);
-
-       config->tile_config_ptr = adev->gfx.config.tile_mode_array;
-       config->num_tile_configs =
-                       ARRAY_SIZE(adev->gfx.config.tile_mode_array);
-       config->macro_tile_config_ptr =
-                       adev->gfx.config.macrotile_mode_array;
-       config->num_macro_tile_configs =
-                       ARRAY_SIZE(adev->gfx.config.macrotile_mode_array);
-
-       return 0;
-}
-
 static inline struct amdgpu_device *get_amdgpu_device(struct kgd_dev *kgd)
 {
        return (struct amdgpu_device *)kgd;
@@ -730,7 +705,6 @@ const struct kfd2kgd_calls gfx_v7_kfd2kgd = {
        .address_watch_get_offset = kgd_address_watch_get_offset,
        .get_atc_vmid_pasid_mapping_info = get_atc_vmid_pasid_mapping_info,
        .set_scratch_backing_va = set_scratch_backing_va,
-       .get_tile_config = get_tile_config,
        .set_vm_context_page_table_base = set_vm_context_page_table_base,
        .read_vmid_from_vmfault_reg = read_vmid_from_vmfault_reg,
 };
index 19a10db..ccd635b 100644 (file)
@@ -41,31 +41,6 @@ enum hqd_dequeue_request_type {
        RESET_WAVES
 };
 
-/* Because of REG_GET_FIELD() being used, we put this function in the
- * asic specific file.
- */
-static int get_tile_config(struct kgd_dev *kgd,
-               struct tile_config *config)
-{
-       struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
-
-       config->gb_addr_config = adev->gfx.config.gb_addr_config;
-       config->num_banks = REG_GET_FIELD(adev->gfx.config.mc_arb_ramcfg,
-                               MC_ARB_RAMCFG, NOOFBANK);
-       config->num_ranks = REG_GET_FIELD(adev->gfx.config.mc_arb_ramcfg,
-                               MC_ARB_RAMCFG, NOOFRANKS);
-
-       config->tile_config_ptr = adev->gfx.config.tile_mode_array;
-       config->num_tile_configs =
-                       ARRAY_SIZE(adev->gfx.config.tile_mode_array);
-       config->macro_tile_config_ptr =
-                       adev->gfx.config.macrotile_mode_array;
-       config->num_macro_tile_configs =
-                       ARRAY_SIZE(adev->gfx.config.macrotile_mode_array);
-
-       return 0;
-}
-
 static inline struct amdgpu_device *get_amdgpu_device(struct kgd_dev *kgd)
 {
        return (struct amdgpu_device *)kgd;
@@ -676,6 +651,5 @@ const struct kfd2kgd_calls gfx_v8_kfd2kgd = {
        .get_atc_vmid_pasid_mapping_info =
                        get_atc_vmid_pasid_mapping_info,
        .set_scratch_backing_va = set_scratch_backing_va,
-       .get_tile_config = get_tile_config,
        .set_vm_context_page_table_base = set_vm_context_page_table_base,
 };
index 7f91fef..df841c2 100644 (file)
@@ -48,28 +48,6 @@ enum hqd_dequeue_request_type {
        RESET_WAVES
 };
 
-
-/* Because of REG_GET_FIELD() being used, we put this function in the
- * asic specific file.
- */
-int kgd_gfx_v9_get_tile_config(struct kgd_dev *kgd,
-               struct tile_config *config)
-{
-       struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
-
-       config->gb_addr_config = adev->gfx.config.gb_addr_config;
-
-       config->tile_config_ptr = adev->gfx.config.tile_mode_array;
-       config->num_tile_configs =
-                       ARRAY_SIZE(adev->gfx.config.tile_mode_array);
-       config->macro_tile_config_ptr =
-                       adev->gfx.config.macrotile_mode_array;
-       config->num_macro_tile_configs =
-                       ARRAY_SIZE(adev->gfx.config.macrotile_mode_array);
-
-       return 0;
-}
-
 static inline struct amdgpu_device *get_amdgpu_device(struct kgd_dev *kgd)
 {
        return (struct amdgpu_device *)kgd;
@@ -736,7 +714,6 @@ const struct kfd2kgd_calls gfx_v9_kfd2kgd = {
        .address_watch_get_offset = kgd_gfx_v9_address_watch_get_offset,
        .get_atc_vmid_pasid_mapping_info =
                        kgd_gfx_v9_get_atc_vmid_pasid_mapping_info,
-       .get_tile_config = kgd_gfx_v9_get_tile_config,
        .set_vm_context_page_table_base = kgd_gfx_v9_set_vm_context_page_table_base,
        .get_hive_id = amdgpu_amdkfd_get_hive_id,
        .get_unique_id = amdgpu_amdkfd_get_unique_id,
index 63d3e66..aedf67d 100644 (file)
@@ -60,5 +60,3 @@ uint32_t kgd_gfx_v9_address_watch_get_offset(struct kgd_dev *kgd,
 
 bool kgd_gfx_v9_get_atc_vmid_pasid_mapping_info(struct kgd_dev *kgd,
                                        uint8_t vmid, uint16_t *p_pasid);
-int kgd_gfx_v9_get_tile_config(struct kgd_dev *kgd,
-               struct tile_config *config);
index e1d1eed..e4481ca 100644 (file)
@@ -2242,3 +2242,25 @@ int amdgpu_amdkfd_remove_gws_from_process(void *info, void *mem)
        kfree(mem);
        return 0;
 }
+
+/* Returns GPU-specific tiling mode information */
+int amdgpu_amdkfd_get_tile_config(struct kgd_dev *kgd,
+                               struct tile_config *config)
+{
+       struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
+
+       config->gb_addr_config = adev->gfx.config.gb_addr_config;
+       config->tile_config_ptr = adev->gfx.config.tile_mode_array;
+       config->num_tile_configs =
+                       ARRAY_SIZE(adev->gfx.config.tile_mode_array);
+       config->macro_tile_config_ptr =
+                       adev->gfx.config.macrotile_mode_array;
+       config->num_macro_tile_configs =
+                       ARRAY_SIZE(adev->gfx.config.macrotile_mode_array);
+
+       /* Those values are not set from GFX9 onwards */
+       config->num_banks = adev->gfx.config.num_banks;
+       config->num_ranks = adev->gfx.config.num_ranks;
+
+       return 0;
+}
index 8d56afd..0ec5f25 100644 (file)
@@ -1169,7 +1169,7 @@ static int kfd_ioctl_get_tile_config(struct file *filep,
        if (!dev)
                return -EINVAL;
 
-       dev->kfd2kgd->get_tile_config(dev->kgd, &config);
+       amdgpu_amdkfd_get_tile_config(dev->kgd, &config);
 
        args->gb_addr_config = config.gb_addr_config;
        args->num_banks = config.num_banks;
index abc0eb4..0cee79d 100644 (file)
@@ -223,8 +223,6 @@ struct tile_config {
  * @set_scratch_backing_va: Sets VA for scratch backing memory of a VMID.
  * Only used for no cp scheduling mode
  *
- * @get_tile_config: Returns GPU-specific tiling mode information
- *
  * @set_vm_context_page_table_base: Program page table base for a VMID
  *
  * @invalidate_tlbs: Invalidate TLBs for a specific PASID
@@ -310,8 +308,6 @@ struct kfd2kgd_calls {
        void (*set_scratch_backing_va)(struct kgd_dev *kgd,
                                uint64_t va, uint32_t vmid);
 
-       int (*get_tile_config)(struct kgd_dev *kgd, struct tile_config *config);
-
        void (*set_vm_context_page_table_base)(struct kgd_dev *kgd,
                        uint32_t vmid, uint64_t page_table_base);
        uint32_t (*read_vmid_from_vmfault_reg)(struct kgd_dev *kgd);