LF-2769-1 mx7dsabresd: Reserve top 1MB DDR for RPMSG usage

When booting with M4 RPMSG demo in u-boot, the M4 will use top 1MB
DDR for RPMSG vring buffer. This overlaps with u-boot MMU table and
modifies some MMU entries.
On mx7dsabresd, this cause u-boot failed to access LCDIF registers
due to the wrong MMU entries.

Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
(cherry picked from commit 8a03d17c92cc04765c6b93f716ea081486fd15f0)
(cherry picked from commit b44fab8da91e4f74a3ab7e537368644ea1a25873)

diff --git a/board/freescale/mx7dsabresd/mx7dsabresd.c b/board/freescale/mx7dsabresd/mx7dsabresd.c
index 10d31c2..c418b13 100644 (file)
--- a/board/freescale/mx7dsabresd/mx7dsabresd.c
+++ b/board/freescale/mx7dsabresd/mx7dsabresd.c
@@ -229,6 +229,14 @@ static void setup_iomux_uart(void)
        imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
 }
 
+#ifdef CONFIG_IMX_BOOTAUX
+ulong board_get_usable_ram_top(ulong total_size)
+{
+       /* Reserve top 1M memory used by M core vring/buffer */
+       return gd->ram_top - SZ_1M;
+}
+#endif
+
 #ifdef CONFIG_FEC_MXC
 static int setup_fec(void)
 {