drm/amdgpu: add gmc ip block for navy_flounder

navy_flounder has similar gc IP version with sienna_cichlid,
follow its setting for the moment.

Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com>
Reviewed-by: Tao Zhou <Tao.Zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
index 2bf112f..55fedad 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
@@ -693,7 +693,8 @@ static void gmc_v10_0_vram_gtt_location(struct amdgpu_device *adev,
 {
        u64 base = 0;
 
-       if (adev->asic_type == CHIP_SIENNA_CICHLID)
+       if (adev->asic_type == CHIP_SIENNA_CICHLID ||
+           adev->asic_type == CHIP_NAVY_FLOUNDER)
                base = gfxhub_v2_1_get_fb_location(adev);
        else
                base = gfxhub_v2_0_get_fb_location(adev);
@@ -705,7 +706,8 @@ static void gmc_v10_0_vram_gtt_location(struct amdgpu_device *adev,
        amdgpu_gmc_gart_location(adev, mc);
 
        /* base offset of vram pages */
-       if (adev->asic_type == CHIP_SIENNA_CICHLID)
+       if (adev->asic_type == CHIP_SIENNA_CICHLID ||
+           adev->asic_type == CHIP_NAVY_FLOUNDER)
                adev->vm_manager.vram_base_offset = gfxhub_v2_1_get_mc_fb_offset(adev);
        else
                adev->vm_manager.vram_base_offset = gfxhub_v2_0_get_mc_fb_offset(adev);
@@ -822,7 +824,8 @@ static int gmc_v10_0_sw_init(void *handle)
        int r, vram_width = 0, vram_type = 0, vram_vendor = 0;
        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
-       if (adev->asic_type == CHIP_SIENNA_CICHLID)
+       if (adev->asic_type == CHIP_SIENNA_CICHLID ||
+           adev->asic_type == CHIP_NAVY_FLOUNDER)
                gfxhub_v2_1_init(adev);
        else
                gfxhub_v2_0_init(adev);
@@ -980,7 +983,8 @@ static int gmc_v10_0_gart_enable(struct amdgpu_device *adev)
        if (r)
                return r;
 
-       if (adev->asic_type == CHIP_SIENNA_CICHLID)
+       if (adev->asic_type == CHIP_SIENNA_CICHLID ||
+           adev->asic_type == CHIP_NAVY_FLOUNDER)
                r = gfxhub_v2_1_gart_enable(adev);
        else
                r = gfxhub_v2_0_gart_enable(adev);
@@ -1004,7 +1008,8 @@ static int gmc_v10_0_gart_enable(struct amdgpu_device *adev)
        value = (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) ?
                false : true;
 
-       if (adev->asic_type == CHIP_SIENNA_CICHLID)
+       if (adev->asic_type == CHIP_SIENNA_CICHLID ||
+           adev->asic_type == CHIP_NAVY_FLOUNDER)
                gfxhub_v2_1_set_fault_enable_default(adev, value);
        else
                gfxhub_v2_0_set_fault_enable_default(adev, value);
@@ -1045,7 +1050,8 @@ static int gmc_v10_0_hw_init(void *handle)
  */
 static void gmc_v10_0_gart_disable(struct amdgpu_device *adev)
 {
-       if (adev->asic_type == CHIP_SIENNA_CICHLID)
+       if (adev->asic_type == CHIP_SIENNA_CICHLID ||
+           adev->asic_type == CHIP_NAVY_FLOUNDER)
                gfxhub_v2_1_gart_disable(adev);
        else
                gfxhub_v2_0_gart_disable(adev);

diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
index e5417c5..07f9d61 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/nv.c
+++ b/drivers/gpu/drm/amd/amdgpu/nv.c
@@ -525,6 +525,7 @@ int nv_set_ip_blocks(struct amdgpu_device *adev)
                break;
        case CHIP_NAVY_FLOUNDER:
                amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
+               amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
                break;
        default:
                return -EINVAL;