ARM: dts: Add C0P2-H0.1 pins mux.

Signed-off-by: Josep Orga <jorga@somdevices.com>

diff --git a/arch/arm/boot/dts/imx6ull-somdevices.dtsi b/arch/arm/boot/dts/imx6ull-somdevices.dtsi
index a85cb43..1337ef1 100644 (file)
--- a/arch/arm/boot/dts/imx6ull-somdevices.dtsi
+++ b/arch/arm/boot/dts/imx6ull-somdevices.dtsi
@@ -38,7 +38,7 @@
 
        backlight {
                compatible = "pwm-backlight";
-               pwms = <&pwm1 0 5000000>;
+               pwms = <&pwm1 0 2000000>;
                brightness-levels = <0 4 8 16 32 64 128 255>;
                default-brightness-level = <6>;
                status = "okay";
@@ -172,9 +172,23 @@
        pinctrl-0 = <&pinctrl_hog_1>;
        pinctrl_hog_1: hoggrp-1 {
                fsl,pins = <
-                       MX6UL_PAD_UART1_RTS_B__GPIO1_IO19       0x17059 /* SD1 CD */
-                       MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT    0x17059 /* SD1 VSELECT */
-                       MX6UL_PAD_GPIO1_IO09__GPIO1_IO09        0x17059 /* SD1 RESET */
+                       MX6UL_PAD_UART1_RTS_B__GPIO1_IO19       0x17059 //WIFI_IRQ
+
+                       /* SOMDEVICES GPIOs */
+                       MX6UL_PAD_NAND_DQS__GPIO4_IO16          0x1b0b0 //GPIO00
+                       MX6UL_PAD_NAND_CE0_B__GPIO4_IO13        0x1b0b0 //GPIO01
+                       MX6UL_PAD_GPIO1_IO02__GPIO1_IO02        0x1b0b0 //GPIO02
+                       MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25     0x1b0b0 //GPIO03
+                       MX6UL_PAD_NAND_CE1_B__GPIO4_IO14        0x1b0b0 //GPIO04
+                       MX6UL_PAD_GPIO1_IO08__GPIO1_IO08        0x1b0b0 //GPIO05
+                       MX6UL_PAD_JTAG_MOD__GPIO1_IO10          0x1b0b0 //GPIO06
+                       MX6UL_PAD_UART1_CTS_B__GPIO1_IO18       0x1b0b0 //GPIO07
+                       MX6UL_PAD_GPIO1_IO09__GPIO1_IO09        0x1b0b0 //GPIO08
+                       MX6UL_PAD_NAND_CLE__GPIO4_IO15          0x1b0b0 //GPIO09
+                       MX6UL_PAD_NAND_WP_B__GPIO4_IO11         0x1b0b0 //GPIO10
+                       MX6UL_PAD_NAND_READY_B__GPIO4_IO12      0x1b0b0 //GPIO11
+                       /* WiFi 32K CLK */
+                       MX6UL_PAD_GPIO1_IO03__OSC32K_32K_OUT 0x1b0b0
                >;
        };
 
@@ -244,8 +258,8 @@
 
        pinctrl_i2c2: i2c2grp {
                fsl,pins = <
-                       MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0
-                       MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0
+                       MX6UL_PAD_GPIO1_IO00__I2C2_SCL 0x4001b8b0
+                       MX6UL_PAD_GPIO1_IO01__I2C2_SDA 0x4001b8b0
                >;
        };
 
@@ -314,8 +328,8 @@
                fsl,pins = <
                        MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX   0x1b0b1
                        MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX   0x1b0b1
-                       MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS  0x1b0b1
-                       MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS  0x1b0b1
+                       MX6UL_PAD_UART2_RTS_B__UART2_DCE_RTS    0x1b0b1
+                       MX6UL_PAD_UART2_CTS_B__UART2_DCE_CTS    0x1b0b1
                >;
        };
 
@@ -323,14 +337,14 @@
                fsl,pins = <
                        MX6UL_PAD_UART2_TX_DATA__UART2_DTE_RX   0x1b0b1
                        MX6UL_PAD_UART2_RX_DATA__UART2_DTE_TX   0x1b0b1
-                       MX6UL_PAD_UART3_RX_DATA__UART2_DTE_CTS  0x1b0b1
-                       MX6UL_PAD_UART3_TX_DATA__UART2_DTE_RTS  0x1b0b1
+                       MX6UL_PAD_UART2_RTS_B__UART2_DTE_CTS    0x1b0b1
+                       MX6UL_PAD_UART2_CTS_B__UART2_DTE_RTS    0x1b0b1
                >;
        };
 
        pinctrl_usb_otg1_id: usbotg1idgrp {
                fsl,pins = <
-                       MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID    0x17059
+                       MX6UL_PAD_UART3_TX_DATA__ANATOP_OTG1_ID 0x17059
                >;
        };
 
@@ -436,7 +450,12 @@
        imx6ul-evk {
                pinctrl_hog_2: hoggrp-2 {
                        fsl,pins = <
-                               MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00      0x80000000
+                               MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00             0x1b0b0 //NAND_nCE2
+                               MX6ULL_PAD_SNVS_TAMPER1__GPIO5_IO01             0x1b0b0 //NAND_nCE3
+                               MX6ULL_PAD_SNVS_TAMPER2__GPIO5_IO02             0x1b0b0 //SDIO_WP
+                               MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03             0x1b0b0 //USB1_EN
+                               MX6ULL_PAD_SNVS_TAMPER4__GPIO5_IO04             0x1b0b0 //USB2_EN
+                               MX6ULL_PAD_SNVS_TAMPER5__GPIO5_IO05             0x1b0b0 //SDIO_PWR_EN
                                MX6ULL_PAD_BOOT_MODE0__GPIO5_IO10               0x1b0b0 //FEC1
                                MX6ULL_PAD_BOOT_MODE1__GPIO5_IO11               0x1b0b0 //FEC2
                        >;