arm64: dts: Added imx8mm-evk.dts features to imx8mm-somdevices.dtsi.

Signed-off-by: Josep Orga <jorga@somdevices.com>

diff --git a/arch/arm64/boot/dts/freescale/imx8mm-somdevices.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-somdevices.dtsi
index 468f65b..7e9bb4e 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8mm-somdevices.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm-somdevices.dtsi
@@ -9,6 +9,9 @@
 #include "imx8mm.dtsi"
 
 / {
+       model = "FSL i.MX8MM µSMARC SOMDEVICES board";
+       compatible = "fsl,imx8mm-somdevices", "fsl,imx8mm";
+
        chosen {
                stdout-path = &uart2;
        };
@@ -170,6 +173,13 @@
                cpu-dai = <&micfil>;
        };
 
+       usdhc1_pwrseq: usdhc1_pwrseq {
+               compatible = "mmc-pwrseq-simple";
+               pinctrl-names = "default";
+               pinctrl-0 = <&pinctrl_usdhc1_gpio>;
+               reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;
+       };
+
 };
 
 &A53_0 {
@@ -188,6 +198,26 @@
        cpu-supply = <&buck2_reg>;
 };
 
+&ddrc {
+       operating-points-v2 = <&ddrc_opp_table>;
+
+       ddrc_opp_table: opp-table {
+               compatible = "operating-points-v2";
+
+               opp-25M {
+                       opp-hz = /bits/ 64 <25000000>;
+               };
+
+               opp-100M {
+                       opp-hz = /bits/ 64 <100000000>;
+               };
+
+               opp-750M {
+                       opp-hz = /bits/ 64 <750000000>;
+               };
+       };
+};
+
 &csi1_bridge {
        fsl,mipi-mode;
        status = "okay";
@@ -672,6 +702,27 @@
        };
 };
 
+&usdhc1 {
+       pinctrl-names = "default", "state_100mhz", "state_200mhz";
+       pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_wlan>;
+       pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_wlan>;
+       pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_wlan>;
+       bus-width = <4>;
+       cap-power-off-card;
+       pm-ignore-notify;
+       keep-power-in-suspend;
+       non-removable;
+       mmc-pwrseq = <&usdhc1_pwrseq>;
+       status = "okay";
+
+       wifi_wake_host {
+               compatible = "nxp,wifi-wake-host";
+               interrupt-parent = <&gpio2>;
+               interrupts = <9 IRQ_TYPE_LEVEL_LOW>;
+               interrupt-names = "host-wake";
+       };
+};
+
 &usdhc2 {
        assigned-clocks = <&clk IMX8MM_CLK_USDHC2>;
        assigned-clock-rates = <200000000>;
@@ -685,6 +736,18 @@
        status = "okay";
 };
 
+&usdhc3 {
+       assigned-clocks = <&clk IMX8MM_CLK_USDHC3_ROOT>;
+       assigned-clock-rates = <400000000>;
+       pinctrl-names = "default", "state_100mhz", "state_200mhz";
+       pinctrl-0 = <&pinctrl_usdhc3>;
+       pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
+       pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
+       bus-width = <8>;
+       non-removable;
+       status = "okay";
+};
+
 &vpu_g1 {
        status = "okay";
 };
@@ -1027,9 +1090,65 @@
                >;
        };
 
+       pinctrl_usdhc3: usdhc3grp {
+               fsl,pins = <
+                       MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK               0x190
+                       MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD               0x1d0
+                       MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0           0x1d0
+                       MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1           0x1d0
+                       MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2           0x1d0
+                       MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2           0x1d0
+                       MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3           0x1d0
+                       MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4             0x1d0
+                       MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5            0x1d0
+                       MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6            0x1d0
+                       MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7              0x1d0
+                       MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE           0x190
+               >;
+       };
+
+       pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
+               fsl,pins = <
+                       MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK               0x194
+                       MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD               0x1d4
+                       MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0           0x1d4
+                       MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1           0x1d4
+                       MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2           0x1d4
+                       MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3           0x1d4
+                       MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4             0x1d4
+                       MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5            0x1d4
+                       MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6            0x1d4
+                       MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7              0x1d4
+                       MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE           0x194
+               >;
+       };
+
+       pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
+               fsl,pins = <
+                       MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK               0x196
+                       MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD               0x1d6
+                       MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0           0x1d6
+                       MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1           0x1d6
+                       MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2           0x1d6
+                       MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3           0x1d6
+                       MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4             0x1d6
+                       MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5            0x1d6
+                       MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6            0x1d6
+                       MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7              0x1d6
+                       MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE           0x196
+               >;
+       };
+
        pinctrl_wdog: wdoggrp {
                fsl,pins = <
                        MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B    0xc6
                >;
        };
+
+       pinctrl_wlan: wlangrp {
+               fsl,pins = <
+                       MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K      0x141
+                       MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9                0x159
+               >;
+       };
 };