MLK-13362 ARM: imx: fix audio bus mode hang on imx6sx/ul/sll

When MMDC runs at a low frequency, it is not recommended to
perform "force measurement", the MMDC measure unit may return
a wrong measurement value when running below 100MHz.

Additionally, the double MU count operations should be only done
when changing the MMDC frequency from 400MHz to a low
frequency(100MHz or 24MHz). Otherwise, the MU count may overflow
and lead to system hang issue.

Signed-off-by: Bai Ping <ping.bai@nxp.com>

diff --git a/arch/arm/mach-imx/busfreq_lpddr2.c b/arch/arm/mach-imx/busfreq_lpddr2.c
index 5bc1807..bda2325 100644 (file)
--- a/arch/arm/mach-imx/busfreq_lpddr2.c
+++ b/arch/arm/mach-imx/busfreq_lpddr2.c
@@ -137,8 +137,13 @@ int update_lpddr2_freq(int ddr_rate)
        ttbr1 = save_ttbr1();
 
        /* Now change DDR frequency. */
-       mx6_change_lpddr2_freq(ddr_rate,
-               (mode == BUS_FREQ_LOW || mode == BUS_FREQ_ULTRA_LOW) ? 1 : 0);
+       if (cpu_is_imx6sl())
+               mx6_change_lpddr2_freq(ddr_rate,
+                       (mode == BUS_FREQ_LOW || mode == BUS_FREQ_ULTRA_LOW) ? 1 : 0);
+       else
+               mx6_change_lpddr2_freq(ddr_rate,
+                       (mode == BUS_FREQ_LOW || mode == BUS_FREQ_AUDIO) ? 1 : 0);
+
        restore_ttbr1(ttbr1);
 
        curr_ddr_rate = ddr_rate;

diff --git a/arch/arm/mach-imx/lpddr2_freq_imx6.S b/arch/arm/mach-imx/lpddr2_freq_imx6.S
index 2e7843c..a7f3877 100644 (file)
--- a/arch/arm/mach-imx/lpddr2_freq_imx6.S
+++ b/arch/arm/mach-imx/lpddr2_freq_imx6.S
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2012-2015 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright (C) 2012-2016 Freescale Semiconductor, Inc. All Rights Reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -300,16 +300,6 @@ mmdc_podf1:
        bic     r6, r6, r4
        orr     r6, r6, r7
        str     r6, [r8, r5]
-       /* Now perform a Force Measurement. */
-       ldr     r6, [r8, r5]
-       orr     r6, r6, #0x800
-       str     r6, [r8, r5]
-       /* Wait for FRC_MSR to clear. */
-force_measure:
-       ldr     r6, [r8, r5]
-       and     r6, r6, #0x800
-       cmp     r6, #0x0
-       bne     force_measure
 
        .endm
 

diff --git a/arch/arm/mach-imx/lpddr2_freq_imx6sll.S b/arch/arm/mach-imx/lpddr2_freq_imx6sll.S
index 3feb28a..edc115c 100644 (file)
--- a/arch/arm/mach-imx/lpddr2_freq_imx6sll.S
+++ b/arch/arm/mach-imx/lpddr2_freq_imx6sll.S
@@ -26,6 +26,8 @@
 #define MMDC0_MAPSR    0x404
 #define MMDC0_MADPCR0  0x410
 
+#define HIGH_BUS_MODE  0x0
+
        .macro  wait_for_ccm_handshake
 
 1:
@@ -125,6 +127,9 @@ skip_periph2_clk2_switch_400m:
        .endm
 
        .macro  mmdc_clk_lower_100MHz
+       /* if MMDC is not in 400MHz mode, skip double mu count */
+       cmp     r1, #HIGH_BUS_MODE
+       bne     1f
 
        /*
         * Prior to reducing the DDR frequency (at 528/400 MHz),
@@ -155,23 +160,13 @@ skip_periph2_clk2_switch_400m:
        bic     r6, r6, r4
        orr     r6, r6, r7
        str     r6, [r5, r8]
-       /* Now perform a Force Measurement. */
-       ldr     r6, [r5, r8]
-       orr     r6, r6, #0x800
-       str     r6, [r5, r8]
-       /* Wait for FRC_MSR to clear. */
-force_measure:
-       ldr     r6, [r5, r8]
-       and     r6, r6, #0x800
-       cmp     r6, #0x0
-       bne     force_measure
 
        /* For freq lower than 100MHz, need to set RALAT to 2 */
        ldr     r6, [r5, #0x18]
        bic     r6, r6, #(0x7 << 6)
        orr     r6, r6, #(0x2 << 6)
        str     r6, [r5, #0x18]
-
+1:
        .endm
 
        .macro  mmdc_clk_above_100MHz

diff --git a/arch/arm/mach-imx/lpddr2_freq_imx6sx.S b/arch/arm/mach-imx/lpddr2_freq_imx6sx.S
index 2c78aac..3155534 100644 (file)
--- a/arch/arm/mach-imx/lpddr2_freq_imx6sx.S
+++ b/arch/arm/mach-imx/lpddr2_freq_imx6sx.S
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2014-2015 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright (C) 2014-2016 Freescale Semiconductor, Inc. All Rights Reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -26,6 +26,8 @@
 #define MMDC0_MAPSR    0x404
 #define MMDC0_MADPCR0  0x410
 
+#define HIGH_BUS_MODE  0x0
+
        /* Check if the cpu is cortex-a7 */
        .macro is_ca7
 
@@ -137,6 +139,9 @@ skip_periph2_clk2_switch_400m:
        .endm
 
        .macro  mmdc_clk_lower_100MHz
+       /* if MMDC is not in 400MHz mode, skip double mu count */
+       cmp     r1, #HIGH_BUS_MODE
+       bne     1f
 
        /*
         * Prior to reducing the DDR frequency (at 528/400 MHz),
@@ -167,23 +172,13 @@ skip_periph2_clk2_switch_400m:
        bic     r6, r6, r4
        orr     r6, r6, r7
        str     r6, [r5, r8]
-       /* Now perform a Force Measurement. */
-       ldr     r6, [r5, r8]
-       orr     r6, r6, #0x800
-       str     r6, [r5, r8]
-       /* Wait for FRC_MSR to clear. */
-force_measure:
-       ldr     r6, [r5, r8]
-       and     r6, r6, #0x800
-       cmp     r6, #0x0
-       bne     force_measure
 
        /* For freq lower than 100MHz, need to set RALAT to 2 */
        ldr     r6, [r5, #0x18]
        bic     r6, r6, #(0x7 << 6)
        orr     r6, r6, #(0x2 << 6)
        str     r6, [r5, #0x18]
-
+1:
        .endm
 
        .macro  mmdc_clk_above_100MHz