ARM: dts: Add support to single/dual ethernet.

Signed-off-by: Josep Orga <jorga@somdevices.com>

diff --git a/arch/arm/boot/dts/imx6ull-somdevices-C0P1.dts b/arch/arm/boot/dts/imx6ull-somdevices-C0P1.dts
index d88d045..6df790f 100644 (file)
--- a/arch/arm/boot/dts/imx6ull-somdevices-C0P1.dts
+++ b/arch/arm/boot/dts/imx6ull-somdevices-C0P1.dts
@@ -1 +1,3 @@
+#define DUAL_ETH
+
 #include "imx6ull-somdevices.dtsi"

diff --git a/arch/arm/boot/dts/imx6ull-somdevices.dtsi b/arch/arm/boot/dts/imx6ull-somdevices.dtsi
index f53c7fd..f3d1322 100644 (file)
--- a/arch/arm/boot/dts/imx6ull-somdevices.dtsi
+++ b/arch/arm/boot/dts/imx6ull-somdevices.dtsi
@@ -5,7 +5,7 @@
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
  */
-
+/* #define DUAL_ETH */
 /dts-v1/;
 
 #include <dt-bindings/input/input.h>
@@ -169,40 +169,67 @@
 
 &fec1 {
        pinctrl-names = "default";
+#ifdef DUAL_ETH
        pinctrl-0 = <&pinctrl_enet1>;
+#else
+       pinctrl-0 = <&pinctrl_enet1 &pinctrl_enet1_mdio>;
+#endif
        phy-mode = "rmii";
        phy-handle = <&ethphy0>;
+       phy-reset-gpios = <&gpio5 10 GPIO_ACTIVE_LOW>;
+       phy-reset-duration = <26>;
+       phy-reset-in-suspend;
        status = "okay";
+
+#ifndef DUAL_ETH
+       mdio {
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               ethphy0: ethernet-phy@0 {
+                       compatible = "ethernet-phy-ieee802.3-c22";
+                       smsc,disable-energy-detect;
+                       reg = <0>;
+                       clocks = <&clks IMX6UL_CLK_ENET_REF>;
+                       clock-names = "rmii-ref";
+               };
+       };
+#endif
 };
 
+#ifdef DUAL_ETH
 &fec2 {
        pinctrl-names = "default";
-       pinctrl-0 = <&pinctrl_enet2>;
+       pinctrl-0 = <&pinctrl_enet2 &pinctrl_enet2_mdio>;
        phy-mode = "rmii";
        phy-handle = <&ethphy1>;
+       phy-reset-gpios = <&gpio5 11 GPIO_ACTIVE_LOW>;
+       phy-reset-duration = <26>;
+       phy-reset-in-suspend;
        status = "okay";
 
        mdio {
                #address-cells = <1>;
                #size-cells = <0>;
 
-               ethphy0: ethernet-phy@2 {
+               ethphy0: ethernet-phy@0 {
                        compatible = "ethernet-phy-ieee802.3-c22";
-                       reg = <2>;
-                       micrel,led-mode = <1>;
+                       smsc,disable-energy-detect;
+                       reg = <0>;
                        clocks = <&clks IMX6UL_CLK_ENET_REF>;
                        clock-names = "rmii-ref";
                };
 
                ethphy1: ethernet-phy@1 {
                        compatible = "ethernet-phy-ieee802.3-c22";
+                       smsc,disable-energy-detect;
                        reg = <1>;
-                       micrel,led-mode = <1>;
                        clocks = <&clks IMX6UL_CLK_ENET2_REF>;
                        clock-names = "rmii-ref";
                };
        };
 };
+#endif
 
 &flexcan1 {
        pinctrl-names = "default";
@@ -325,8 +352,6 @@
 
        pinctrl_enet2: enet2grp {
                fsl,pins = <
-                       MX6UL_PAD_GPIO1_IO07__ENET2_MDC         0x1b0b0
-                       MX6UL_PAD_GPIO1_IO06__ENET2_MDIO        0x1b0b0
                        MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN      0x1b0b0
                        MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER      0x1b0b0
                        MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
@@ -338,6 +363,20 @@
                >;
        };
 
+       pinctrl_enet1_mdio: mdioenet1grp {
+               fsl,pins = <
+                       MX6UL_PAD_GPIO1_IO07__ENET1_MDC         0x1b0b0
+                       MX6UL_PAD_GPIO1_IO06__ENET1_MDIO        0x1b0b0
+               >;
+       };
+
+       pinctrl_enet2_mdio: mdioenet2grp {
+               fsl,pins = <
+                       MX6UL_PAD_GPIO1_IO07__ENET2_MDC         0x1b0b0
+                       MX6UL_PAD_GPIO1_IO06__ENET2_MDIO        0x1b0b0
+               >;
+       };
+
        pinctrl_flexcan1: flexcan1grp{
                fsl,pins = <
                        MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX      0x1b020
@@ -574,6 +613,8 @@
                pinctrl_hog_2: hoggrp-2 {
                        fsl,pins = <
                                MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00      0x80000000
+                               MX6ULL_PAD_BOOT_MODE0__GPIO5_IO10               0x1b0b0 //FEC1
+                               MX6ULL_PAD_BOOT_MODE1__GPIO5_IO11               0x1b0b0 //FEC2
                        >;
                };