MLK-22851-4 imx8mm/imx8mn: Enable eMMC HS400ES and SD UHS mode on EVK

Both imx8mn/imx8mm EVK boards have eMMC 5.1 chip and support SD3.0
So we enable the HS400ES and UHS configs to enhance eMMC/SD access.

The change also needs to set usdhc clock to 400Mhz and update compatible
string to fsl,imx8mm-usdhc

Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
(cherry picked from commit cf83fe7dcfcb14dd633ad43ef387793a863e111a)

diff --git a/arch/arm/dts/fsl-imx8mm.dtsi b/arch/arm/dts/fsl-imx8mm.dtsi
index f4f61cf..acffab7 100644 (file)
--- a/arch/arm/dts/fsl-imx8mm.dtsi
+++ b/arch/arm/dts/fsl-imx8mm.dtsi
@@ -685,7 +685,7 @@
        };
 
        usdhc1: mmc@30b40000 {
-               compatible = "fsl,imx8mq-usdhc", "fsl,imx8qm-usdhc";
+               compatible = "fsl,imx8mm-usdhc", "fsl,imx8qm-usdhc";
                reg = <0x0 0x30b40000 0x0 0x10000>;
                interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&clk IMX8MM_CLK_DUMMY>,
@@ -701,7 +701,7 @@
        };
 
        usdhc2: mmc@30b50000 {
-               compatible = "fsl,imx8mq-usdhc", "fsl,imx8qm-usdhc";
+               compatible = "fsl,imx8mm-usdhc", "fsl,imx8qm-usdhc";
                reg = <0x0 0x30b50000 0x0 0x10000>;
                interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&clk IMX8MM_CLK_DUMMY>,
@@ -715,7 +715,7 @@
        };
 
        usdhc3: mmc@30b60000 {
-               compatible = "fsl,imx8mq-usdhc", "fsl,imx8qm-usdhc";
+               compatible = "fsl,imx8mm-usdhc", "fsl,imx8qm-usdhc";
                reg = <0x0 0x30b60000 0x0 0x10000>;
                interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&clk IMX8MM_CLK_DUMMY>,

diff --git a/arch/arm/dts/fsl-imx8mn.dtsi b/arch/arm/dts/fsl-imx8mn.dtsi
index 0fcc770..21247d6 100644 (file)
--- a/arch/arm/dts/fsl-imx8mn.dtsi
+++ b/arch/arm/dts/fsl-imx8mn.dtsi
@@ -515,7 +515,7 @@
        };
 
        usdhc1: mmc@30b40000 {
-               compatible = "fsl,imx8mq-usdhc", "fsl,imx7d-usdhc";
+               compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
                reg = <0x0 0x30b40000 0x0 0x10000>;
                interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&clk IMX8MN_CLK_DUMMY>,
@@ -531,7 +531,7 @@
        };
 
        usdhc2: mmc@30b50000 {
-               compatible = "fsl,imx8mq-usdhc", "fsl,imx7d-usdhc";
+               compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
                reg = <0x0 0x30b50000 0x0 0x10000>;
                interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&clk IMX8MN_CLK_DUMMY>,
@@ -545,7 +545,7 @@
        };
 
        usdhc3: mmc@30b60000 {
-               compatible = "fsl,imx8mq-usdhc", "fsl,imx7d-usdhc";
+               compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
                reg = <0x0 0x30b60000 0x0 0x10000>;
                interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&clk IMX8MN_CLK_DUMMY>,

diff --git a/arch/arm/mach-imx/imx8m/clock_imx8mm.c b/arch/arm/mach-imx/imx8m/clock_imx8mm.c
index 33303f2..869a2f0 100644 (file)
--- a/arch/arm/mach-imx/imx8m/clock_imx8mm.c
+++ b/arch/arm/mach-imx/imx8m/clock_imx8mm.c
@@ -597,22 +597,19 @@ void init_clk_usdhc(u32 index)
        case 0:
                clock_enable(CCGR_USDHC1, 0);
                clock_set_target_val(USDHC1_CLK_ROOT, CLK_ROOT_ON |
-                                    CLK_ROOT_SOURCE_SEL(1) |
-                                    CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2));
+                                    CLK_ROOT_SOURCE_SEL(1));
                clock_enable(CCGR_USDHC1, 1);
                return;
        case 1:
                clock_enable(CCGR_USDHC2, 0);
                clock_set_target_val(USDHC2_CLK_ROOT, CLK_ROOT_ON |
-                                    CLK_ROOT_SOURCE_SEL(1) |
-                                    CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2));
+                                    CLK_ROOT_SOURCE_SEL(1));
                clock_enable(CCGR_USDHC2, 1);
                return;
        case 2:
                clock_enable(CCGR_USDHC3, 0);
                clock_set_target_val(USDHC3_CLK_ROOT, CLK_ROOT_ON |
-                                    CLK_ROOT_SOURCE_SEL(1) |
-                                    CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2));
+                                    CLK_ROOT_SOURCE_SEL(1));
                clock_enable(CCGR_USDHC3, 1);
                return;
        default:

diff --git a/configs/imx8mm_ddr4_evk_defconfig b/configs/imx8mm_ddr4_evk_defconfig
index 97f2e99..981474a 100644 (file)
--- a/configs/imx8mm_ddr4_evk_defconfig
+++ b/configs/imx8mm_ddr4_evk_defconfig
@@ -44,6 +44,8 @@ CONFIG_DM_GPIO=y
 CONFIG_DM_I2C=y
 CONFIG_SYS_I2C_MXC=y
 CONFIG_DM_MMC=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
 # CONFIG_DM_PMIC=y
 CONFIG_EFI_PARTITION=y
 CONFIG_DM_ETH=y

diff --git a/configs/imx8mm_ddr4_evk_nand_defconfig b/configs/imx8mm_ddr4_evk_nand_defconfig
index af92180..1230d56 100644 (file)
--- a/configs/imx8mm_ddr4_evk_nand_defconfig
+++ b/configs/imx8mm_ddr4_evk_nand_defconfig
@@ -42,6 +42,8 @@ CONFIG_DM_GPIO=y
 CONFIG_DM_I2C=y
 CONFIG_SYS_I2C_MXC=y
 CONFIG_DM_MMC=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
 # CONFIG_DM_PMIC=y
 CONFIG_EFI_PARTITION=y
 CONFIG_DM_ETH=y

diff --git a/configs/imx8mm_evk_defconfig b/configs/imx8mm_evk_defconfig
index 7331552..478ddde 100644 (file)
--- a/configs/imx8mm_evk_defconfig
+++ b/configs/imx8mm_evk_defconfig
@@ -45,6 +45,10 @@ CONFIG_DM_GPIO=y
 CONFIG_DM_I2C=y
 CONFIG_SYS_I2C_MXC=y
 CONFIG_DM_MMC=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_MMC_HS400_ES_SUPPORT=y
 # CONFIG_DM_PMIC=y
 CONFIG_EFI_PARTITION=y
 CONFIG_DM_SPI_FLASH=y

diff --git a/configs/imx8mm_evk_fspi_defconfig b/configs/imx8mm_evk_fspi_defconfig
index daa87f5..c68aa94 100644 (file)
--- a/configs/imx8mm_evk_fspi_defconfig
+++ b/configs/imx8mm_evk_fspi_defconfig
@@ -45,6 +45,10 @@ CONFIG_DM_GPIO=y
 CONFIG_DM_I2C=y
 CONFIG_SYS_I2C_MXC=y
 CONFIG_DM_MMC=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_MMC_HS400_ES_SUPPORT=y
 # CONFIG_DM_PMIC=y
 CONFIG_EFI_PARTITION=y
 CONFIG_DM_SPI_FLASH=y

diff --git a/configs/imx8mn_ddr4_evk_defconfig b/configs/imx8mn_ddr4_evk_defconfig
index 8b38fa3..88e6c53 100644 (file)
--- a/configs/imx8mn_ddr4_evk_defconfig
+++ b/configs/imx8mn_ddr4_evk_defconfig
@@ -45,6 +45,10 @@ CONFIG_DM_GPIO=y
 CONFIG_DM_I2C=y
 CONFIG_SYS_I2C_MXC=y
 CONFIG_DM_MMC=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_MMC_HS400_ES_SUPPORT=y
 # CONFIG_DM_PMIC=y
 CONFIG_EFI_PARTITION=y
 CONFIG_DM_SPI_FLASH=y

diff --git a/configs/imx8mn_ddr4_evk_nom_defconfig b/configs/imx8mn_ddr4_evk_nom_defconfig
index cb8c885..9d70fbc 100644 (file)
--- a/configs/imx8mn_ddr4_evk_nom_defconfig
+++ b/configs/imx8mn_ddr4_evk_nom_defconfig
@@ -44,6 +44,10 @@ CONFIG_DM_GPIO=y
 CONFIG_DM_I2C=y
 CONFIG_SYS_I2C_MXC=y
 CONFIG_DM_MMC=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_MMC_HS400_ES_SUPPORT=y
 # CONFIG_DM_PMIC=y
 CONFIG_EFI_PARTITION=y
 CONFIG_DM_SPI_FLASH=y