clk: imx: Rename clk-composite clock to clk-composite-7ulp

The imx/clk-composite is only used by 7ulp. It makes more sense
to mention that in the name of the file and the register function
since later imx-composite clocks may be added.

Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Reviewed-by: Leonard Crestez <leonard.crestez@nxp.com>
Signed-off-by: Arulpandiyan Vadivel <arulpandiyan_vadivel@mentor.com>

diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile
index 57a322b..c834235 100644 (file)
--- a/drivers/clk/imx/Makefile
+++ b/drivers/clk/imx/Makefile
@@ -12,7 +12,6 @@ obj-y += \
        clk-pllv2.o \
        clk-pllv3.o \
        clk-pfd.o \
-       clk-composite.o \
        clk-pllv4.o \
        clk-pllv5.o \
        clk-pfdv2.o
@@ -30,5 +29,5 @@ obj-$(CONFIG_SOC_IMX6SLL) += clk-imx6sll.o
 obj-$(CONFIG_SOC_IMX6SX) += clk-imx6sx.o
 obj-$(CONFIG_SOC_IMX6UL) += clk-imx6ul.o
 obj-$(CONFIG_SOC_IMX7D)  += clk-imx7d.o
-obj-$(CONFIG_SOC_IMX7ULP)  += clk-imx7ulp.o
+obj-$(CONFIG_SOC_IMX7ULP)  += clk-imx7ulp.o clk-composite-7ulp.o
 obj-$(CONFIG_SOC_VF610)  += clk-vf610.o

diff --git a/drivers/clk/imx/clk-composite-7ulp.c b/drivers/clk/imx/clk-composite-7ulp.c
new file mode 100644 (file)
index 0000000..8b65978
--- /dev/null
+++ b/drivers/clk/imx/clk-composite-7ulp.c
@@ -0,0 +1,103 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+#include <linux/errno.h>
+#include <linux/slab.h>
+#include <linux/clk-provider.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+
+#include "clk.h"
+
+#define PCG_PCS_SHIFT  24
+#define PCG_PCS_MASK   0x7
+#define PCG_CGC_SHIFT  30
+#define PCG_FRAC_SHIFT 3
+#define PCG_FRAC_WIDTH 1
+#define PCG_FRAC_MASK  BIT(3)
+#define PCG_PCD_SHIFT  0
+#define PCG_PCD_WIDTH  3
+#define PCG_PCD_MASK   0x7
+
+#define PCG_PREDIV_SHIFT       16
+#define PCG_PREDIV_WIDTH       3
+#define PCG_PREDIV_MAX         8
+
+#define PCG_DIV_SHIFT          0
+#define PCG_DIV_WIDTH          6
+#define PCG_DIV_MAX            64
+
+#define clk_div_mask(width) ((1 << (width)) - 1)
+
+struct clk *imx7ulp_clk_composite(const char *name, const char **parent_names,
+                             int num_parents, bool mux_present,
+                             bool rate_present, bool gate_present,
+                             void __iomem *reg)
+{
+       struct clk_hw *mux_hw = NULL, *fd_hw = NULL, *gate_hw = NULL;
+       struct clk_fractional_divider *fd = NULL;
+       struct clk_gate *gate = NULL;
+       struct clk_mux *mux = NULL;
+       struct clk *clk;
+
+       if (mux_present) {
+               mux = kzalloc(sizeof(*mux), GFP_KERNEL);
+               if (!mux)
+                       return ERR_PTR(-ENOMEM);
+               mux_hw = &mux->hw;
+               mux->reg = reg;
+               mux->shift = PCG_PCS_SHIFT;
+               mux->mask = PCG_PCS_MASK;
+       }
+
+       if (rate_present) {
+               fd = kzalloc(sizeof(*fd), GFP_KERNEL);
+               if (!fd) {
+                       kfree(mux);
+                       return ERR_PTR(-ENOMEM);
+               }
+               fd_hw = &fd->hw;
+               fd->reg = reg;
+               fd->mshift = PCG_FRAC_SHIFT;
+               fd->mwidth = PCG_FRAC_WIDTH;
+               fd->mmask  = PCG_FRAC_MASK;
+               fd->nshift = PCG_PCD_SHIFT;
+               fd->nwidth = PCG_PCD_WIDTH;
+               fd->nmask = PCG_PCD_MASK;
+               fd->flags = CLK_FRAC_DIVIDER_ZERO_BASED;
+       }
+
+       if (gate_present) {
+               gate = kzalloc(sizeof(*gate), GFP_KERNEL);
+               if (!gate) {
+                       kfree(mux);
+                       kfree(fd);
+                       return ERR_PTR(-ENOMEM);
+               }
+               gate_hw = &gate->hw;
+               gate->reg = reg;
+               gate->bit_idx = PCG_CGC_SHIFT;
+       }
+
+       clk = clk_register_composite(NULL, name, parent_names, num_parents,
+                                   mux_hw, &clk_mux_ops, fd_hw,
+                                   &clk_fractional_divider_ops, gate_hw,
+                                   &clk_gate_ops, CLK_SET_RATE_GATE |
+                                   CLK_SET_PARENT_GATE);
+       if (IS_ERR(clk)) {
+               kfree(mux);
+               kfree(fd);
+               kfree(gate);
+       }
+
+       return clk;
+}
+

diff --git a/drivers/clk/imx/clk-composite.c b/drivers/clk/imx/clk-composite.c
deleted file mode 100644 (file)
index c6105d5..0000000
--- a/drivers/clk/imx/clk-composite.c
+++ /dev/null
@@ -1,89 +0,0 @@
-/*
- * Copyright (C) 2016 Freescale Semiconductor, Inc.
- * Copyright 2017 NXP
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-
-#include <linux/clk-provider.h>
-#include <linux/err.h>
-#include <linux/slab.h>
-
-#define PCG_PCS_SHIFT  24
-#define PCG_PCS_MASK   0x7
-#define PCG_CGC_SHIFT  30
-#define PCG_FRAC_SHIFT 3
-#define PCG_FRAC_WIDTH 1
-#define PCG_FRAC_MASK  BIT(3)
-#define PCG_PCD_SHIFT  0
-#define PCG_PCD_WIDTH  3
-#define PCG_PCD_MASK   0x7
-
-struct clk *imx_clk_composite(const char *name, const char **parent_names,
-                             int num_parents, bool mux_present,
-                             bool rate_present, bool gate_present,
-                             void __iomem *reg)
-{
-       struct clk_hw *mux_hw = NULL, *fd_hw = NULL, *gate_hw = NULL;
-       struct clk_fractional_divider *fd = NULL;
-       struct clk_gate *gate = NULL;
-       struct clk_mux *mux = NULL;
-       struct clk *clk;
-
-       if (mux_present) {
-               mux = kzalloc(sizeof(*mux), GFP_KERNEL);
-               if (!mux)
-                       return ERR_PTR(-ENOMEM);
-               mux_hw = &mux->hw;
-               mux->reg = reg;
-               mux->shift = PCG_PCS_SHIFT;
-               mux->mask = PCG_PCS_MASK;
-       }
-
-       if (rate_present) {
-               fd = kzalloc(sizeof(*fd), GFP_KERNEL);
-               if (!fd) {
-                       kfree(mux);
-                       return ERR_PTR(-ENOMEM);
-               }
-               fd_hw = &fd->hw;
-               fd->reg = reg;
-               fd->mshift = PCG_FRAC_SHIFT;
-               fd->mwidth = PCG_FRAC_WIDTH;
-               fd->mmask  = PCG_FRAC_MASK;
-               fd->nshift = PCG_PCD_SHIFT;
-               fd->nwidth = PCG_PCD_WIDTH;
-               fd->nmask = PCG_PCD_MASK;
-               fd->flags = CLK_FRAC_DIVIDER_ZERO_BASED;
-       }
-
-       if (gate_present) {
-               gate = kzalloc(sizeof(*gate), GFP_KERNEL);
-               if (!gate) {
-                       kfree(mux);
-                       kfree(fd);
-                       return ERR_PTR(-ENOMEM);
-               }
-               gate_hw = &gate->hw;
-               gate->reg = reg;
-               gate->bit_idx = PCG_CGC_SHIFT;
-       }
-
-       clk = clk_register_composite(NULL, name, parent_names, num_parents,
-                                   mux_hw, &clk_mux_ops, fd_hw,
-                                   &clk_fractional_divider_ops, gate_hw,
-                                   &clk_gate_ops, CLK_SET_RATE_GATE |
-                                   CLK_SET_PARENT_GATE);
-       if (IS_ERR(clk)) {
-               kfree(mux);
-               kfree(fd);
-               kfree(gate);
-       }
-
-       return clk;
-}

diff --git a/drivers/clk/imx/clk-imx7ulp.c b/drivers/clk/imx/clk-imx7ulp.c
index dc9009b..800ad42 100644 (file)
--- a/drivers/clk/imx/clk-imx7ulp.c
+++ b/drivers/clk/imx/clk-imx7ulp.c
@@ -157,45 +157,45 @@ static void __init imx7ulp_clocks_init(struct device_node *scg_node)
        clks[IMX7ULP_CLK_RGPIO2P1]      = imx_clk_gate("rgpio2p1", "nic1_bus",  base + 0x3c, 30);
        clks[IMX7ULP_CLK_DMA_MUX1]      = imx_clk_gate("dma_mux1", "nic1_bus",  base + 0x84, 30);
        clks[IMX7ULP_CLK_CAAM]          = imx_clk_gate("caam", "nic1_div",      base + 0x90, 30);
-       clks[IMX7ULP_CLK_LPTPM4]        = imx_clk_composite("lptpm4",  periph_bus_sels, ARRAY_SIZE(periph_bus_sels), true, false, true, base + 0x94);
-       clks[IMX7ULP_CLK_LPTPM5]        = imx_clk_composite("lptmp5",  periph_bus_sels, ARRAY_SIZE(periph_bus_sels), true, false, true, base + 0x98);
-       clks[IMX7ULP_CLK_LPIT1]         = imx_clk_composite("lpit1",   periph_bus_sels, ARRAY_SIZE(periph_bus_sels), true, false, true, base + 0x9C);
-       clks[IMX7ULP_CLK_LPSPI2]        = imx_clk_composite("lpspi2",  periph_bus_sels, ARRAY_SIZE(periph_bus_sels), true, false, true, base + 0xA4);
-       clks[IMX7ULP_CLK_LPSPI3]        = imx_clk_composite("lpspi3",  periph_bus_sels, ARRAY_SIZE(periph_bus_sels), true, false, true, base + 0xA8);
-       clks[IMX7ULP_CLK_LPI2C4]        = imx_clk_composite("lpi2c4",  periph_bus_sels, ARRAY_SIZE(periph_bus_sels), true, false, true, base + 0xAC);
-       clks[IMX7ULP_CLK_LPI2C5]        = imx_clk_composite("lpi2c5",  periph_bus_sels, ARRAY_SIZE(periph_bus_sels), true, false, true, base + 0xB0);
-       clks[IMX7ULP_CLK_LPUART4]       = imx_clk_composite("lpuart4", periph_bus_sels, ARRAY_SIZE(periph_bus_sels), true, false, true, base + 0xB4);
-       clks[IMX7ULP_CLK_LPUART5]       = imx_clk_composite("lpuart5", periph_bus_sels, ARRAY_SIZE(periph_bus_sels), true, false, true, base + 0xB8);
-       clks[IMX7ULP_CLK_FLEXIO1]       = imx_clk_composite("flexio",  periph_bus_sels, ARRAY_SIZE(periph_plat_sels), true, false, true, base + 0xC4);
-       clks[IMX7ULP_CLK_USB0]          = imx_clk_composite("usb0",    periph_plat_sels, ARRAY_SIZE(periph_plat_sels), true, true,  true, base + 0xCC);
-       clks[IMX7ULP_CLK_USB1]          = imx_clk_composite("usb1",    periph_plat_sels, ARRAY_SIZE(periph_plat_sels), true, true,  true, base + 0xD0);
+       clks[IMX7ULP_CLK_LPTPM4]        = imx7ulp_clk_composite("lptpm4",  periph_bus_sels, ARRAY_SIZE(periph_bus_sels), true, false, true, base + 0x94);
+       clks[IMX7ULP_CLK_LPTPM5]        = imx7ulp_clk_composite("lptmp5",  periph_bus_sels, ARRAY_SIZE(periph_bus_sels), true, false, true, base + 0x98);
+       clks[IMX7ULP_CLK_LPIT1]         = imx7ulp_clk_composite("lpit1",   periph_bus_sels, ARRAY_SIZE(periph_bus_sels), true, false, true, base + 0x9C);
+       clks[IMX7ULP_CLK_LPSPI2]        = imx7ulp_clk_composite("lpspi2",  periph_bus_sels, ARRAY_SIZE(periph_bus_sels), true, false, true, base + 0xA4);
+       clks[IMX7ULP_CLK_LPSPI3]        = imx7ulp_clk_composite("lpspi3",  periph_bus_sels, ARRAY_SIZE(periph_bus_sels), true, false, true, base + 0xA8);
+       clks[IMX7ULP_CLK_LPI2C4]        = imx7ulp_clk_composite("lpi2c4",  periph_bus_sels, ARRAY_SIZE(periph_bus_sels), true, false, true, base + 0xAC);
+       clks[IMX7ULP_CLK_LPI2C5]        = imx7ulp_clk_composite("lpi2c5",  periph_bus_sels, ARRAY_SIZE(periph_bus_sels), true, false, true, base + 0xB0);
+       clks[IMX7ULP_CLK_LPUART4]       = imx7ulp_clk_composite("lpuart4", periph_bus_sels, ARRAY_SIZE(periph_bus_sels), true, false, true, base + 0xB4);
+       clks[IMX7ULP_CLK_LPUART5]       = imx7ulp_clk_composite("lpuart5", periph_bus_sels, ARRAY_SIZE(periph_bus_sels), true, false, true, base + 0xB8);
+       clks[IMX7ULP_CLK_FLEXIO1]       = imx7ulp_clk_composite("flexio",  periph_bus_sels, ARRAY_SIZE(periph_plat_sels), true, false, true, base + 0xC4);
+       clks[IMX7ULP_CLK_USB0]          = imx7ulp_clk_composite("usb0",    periph_plat_sels, ARRAY_SIZE(periph_plat_sels), true, true,  true, base + 0xCC);
+       clks[IMX7ULP_CLK_USB1]          = imx7ulp_clk_composite("usb1",    periph_plat_sels, ARRAY_SIZE(periph_plat_sels), true, true,  true, base + 0xD0);
        clks[IMX7ULP_CLK_USB_PHY]       = imx_clk_gate("usb_phy",  "nic1_bus", base + 0xD4, 30);
-       clks[IMX7ULP_CLK_USDHC0]        = imx_clk_composite("usdhc0",  periph_plat_sels, ARRAY_SIZE(periph_plat_sels), true, true,  true, base + 0xDC);
-       clks[IMX7ULP_CLK_USDHC1]        = imx_clk_composite("usdhc1",  periph_plat_sels, ARRAY_SIZE(periph_plat_sels), true, true,  true, base + 0xE0);
-       clks[IMX7ULP_CLK_WDG1]          = imx_clk_composite("wdg1",    periph_bus_sels, ARRAY_SIZE(periph_bus_sels), true, true,  true, base + 0xF4);
-       clks[IMX7ULP_CLK_WDG2]          = imx_clk_composite("wdg2",    periph_bus_sels, ARRAY_SIZE(periph_bus_sels), true, true,  true, base + 0x10C);
+       clks[IMX7ULP_CLK_USDHC0]        = imx7ulp_clk_composite("usdhc0",  periph_plat_sels, ARRAY_SIZE(periph_plat_sels), true, true,  true, base + 0xDC);
+       clks[IMX7ULP_CLK_USDHC1]        = imx7ulp_clk_composite("usdhc1",  periph_plat_sels, ARRAY_SIZE(periph_plat_sels), true, true,  true, base + 0xE0);
+       clks[IMX7ULP_CLK_WDG1]          = imx7ulp_clk_composite("wdg1",    periph_bus_sels, ARRAY_SIZE(periph_bus_sels), true, true,  true, base + 0xF4);
+       clks[IMX7ULP_CLK_WDG2]          = imx7ulp_clk_composite("wdg2",    periph_bus_sels, ARRAY_SIZE(periph_bus_sels), true, true,  true, base + 0x10C);
 
        /* PCC3 */
        np = of_find_compatible_node(NULL, NULL, "fsl,imx7ulp-pcc3");
        base = of_iomap(np, 0);
        WARN_ON(!base);
 
-       clks[IMX7ULP_CLK_LPTPM6]        = imx_clk_composite("lptpm6",  periph_bus_sels, ARRAY_SIZE(periph_bus_sels), true, false, true, base + 0x84);
-       clks[IMX7ULP_CLK_LPTPM7]        = imx_clk_composite("lptpm7",  periph_bus_sels, ARRAY_SIZE(periph_bus_sels), true, false, true, base + 0x88);
-       clks[IMX7ULP_CLK_LPI2C6]        = imx_clk_composite("lpi2c6",  periph_bus_sels, ARRAY_SIZE(periph_bus_sels), true, false, true, base + 0x90);
-       clks[IMX7ULP_CLK_LPI2C7]        = imx_clk_composite("lpi2c7",  periph_bus_sels, ARRAY_SIZE(periph_bus_sels), true, false, true, base + 0x94);
-       clks[IMX7ULP_CLK_LPUART6]       = imx_clk_composite("lpuart6", periph_bus_sels, ARRAY_SIZE(periph_bus_sels), true, false, true, base + 0x98);
-       clks[IMX7ULP_CLK_LPUART7]       = imx_clk_composite("lpuart7", periph_bus_sels, ARRAY_SIZE(periph_bus_sels), true, false, true, base + 0x9C);
+       clks[IMX7ULP_CLK_LPTPM6]        = imx7ulp_clk_composite("lptpm6",  periph_bus_sels, ARRAY_SIZE(periph_bus_sels), true, false, true, base + 0x84);
+       clks[IMX7ULP_CLK_LPTPM7]        = imx7ulp_clk_composite("lptpm7",  periph_bus_sels, ARRAY_SIZE(periph_bus_sels), true, false, true, base + 0x88);
+       clks[IMX7ULP_CLK_LPI2C6]        = imx7ulp_clk_composite("lpi2c6",  periph_bus_sels, ARRAY_SIZE(periph_bus_sels), true, false, true, base + 0x90);
+       clks[IMX7ULP_CLK_LPI2C7]        = imx7ulp_clk_composite("lpi2c7",  periph_bus_sels, ARRAY_SIZE(periph_bus_sels), true, false, true, base + 0x94);
+       clks[IMX7ULP_CLK_LPUART6]       = imx7ulp_clk_composite("lpuart6", periph_bus_sels, ARRAY_SIZE(periph_bus_sels), true, false, true, base + 0x98);
+       clks[IMX7ULP_CLK_LPUART7]       = imx7ulp_clk_composite("lpuart7", periph_bus_sels, ARRAY_SIZE(periph_bus_sels), true, false, true, base + 0x9C);
        clks[IMX7ULP_CLK_VIU]           = imx_clk_gate("viu", "nic1_div", base + 0xA0, 30);
-       clks[IMX7ULP_CLK_DSI]           = imx_clk_composite("dsi",     periph_bus_sels, ARRAY_SIZE(periph_bus_sels), true, true,  true, base + 0xA4);
-       clks[IMX7ULP_CLK_LCDIF]         = imx_clk_composite("lcdif",   periph_plat_sels, ARRAY_SIZE(periph_plat_sels), true, true,  true, base + 0xA8);
+       clks[IMX7ULP_CLK_DSI]           = imx7ulp_clk_composite("dsi",     periph_bus_sels, ARRAY_SIZE(periph_bus_sels), true, true,  true, base + 0xA4);
+       clks[IMX7ULP_CLK_LCDIF]         = imx7ulp_clk_composite("lcdif",   periph_plat_sels, ARRAY_SIZE(periph_plat_sels), true, true,  true, base + 0xA8);
        clks[IMX7ULP_CLK_MMDC]          = imx_clk_gate("mmdc", "nic1_div", base + 0xAC, 30);
-       clks[IMX7ULP_CLK_GPU3D]         = imx_clk_composite("gpu3d",   periph_plat_sels, ARRAY_SIZE(periph_plat_sels), true, false, true, base + 0x140);
+       clks[IMX7ULP_CLK_GPU3D]         = imx7ulp_clk_composite("gpu3d",   periph_plat_sels, ARRAY_SIZE(periph_plat_sels), true, false, true, base + 0x140);
        clks[IMX7ULP_CLK_PCTLC]         = imx_clk_gate("pctlc", "nic1_bus", base + 0xb8, 30);
        clks[IMX7ULP_CLK_PCTLD]         = imx_clk_gate("pctld", "nic1_bus", base + 0xbc, 30);
        clks[IMX7ULP_CLK_PCTLE]         = imx_clk_gate("pctle", "nic1_bus", base + 0xc0, 30);
        clks[IMX7ULP_CLK_PCTLF]         = imx_clk_gate("pctlf", "nic1_bus", base + 0xc4, 30);
-       clks[IMX7ULP_CLK_GPU2D]         = imx_clk_composite("gpu2d",   periph_plat_sels, ARRAY_SIZE(periph_plat_sels), true, false, true, base + 0x144);
+       clks[IMX7ULP_CLK_GPU2D]         = imx7ulp_clk_composite("gpu2d",   periph_plat_sels, ARRAY_SIZE(periph_plat_sels), true, false, true, base + 0x144);
 
        imx_check_clocks(clks, ARRAY_SIZE(clks));
 

diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h
index 0c4c607..609b437 100644 (file)
--- a/drivers/clk/imx/clk.h
+++ b/drivers/clk/imx/clk.h
@@ -349,7 +349,7 @@ static inline int clk_on_imx6sx(void)
        return of_machine_is_compatible("fsl,imx6sx");
 }
 
-struct clk *imx_clk_composite(const char *name, const char **parent_name,
+struct clk *imx7ulp_clk_composite(const char *name, const char **parent_name,
                              int num_parents, bool mux_present, bool rate_present,
                              bool gate_present, void __iomem *reg);