MLK-19317-2 drm/bridge: sec-dsim: fine tune for '720p@60Hz' mode on 2 lanes

There is an issue that run several times of modetest 720p@60 test,
display turns to be abnormal or no display. So fine tunning the
DPHY TIMING config to use the same timing config of '720p@60Hz'
mode on 4 data lanes for the same display mode no 2 data lanes.
Until now, it works fine with this config.

Signed-off-by: Fancy Fang <chen.fang@nxp.com>
(cherry picked from commit 6ca115f778cf61691ef4c20d8473e5818f96ad31)
(cherry picked from commit 12740608ad7a6e94b6d1a9bdcffbc96087bb3a3e)

diff --git a/drivers/gpu/drm/bridge/sec-dsim.c b/drivers/gpu/drm/bridge/sec-dsim.c
index 5f3a660..ec7be9a 100644 (file)
--- a/drivers/gpu/drm/bridge/sec-dsim.c
+++ b/drivers/gpu/drm/bridge/sec-dsim.c
@@ -995,9 +995,29 @@ static void sec_mipi_dsim_config_dphy(struct sec_mipi_dsim *dsim)
        const struct sec_mipi_dsim_dphy_timing *match = NULL;
        const struct sec_mipi_dsim_plat_data *pdata = dsim->pdata;
        uint32_t phytiming = 0, phytiming1 = 0, phytiming2 = 0, timeout = 0;
+       uint32_t hactive, vactive;
+       struct videomode *vmode = &dsim->vmode;
+       struct drm_display_mode mode;
 
        key.bit_clk = DIV_ROUND_CLOSEST_ULL(dsim->bit_clk, 1000);
 
+       /* '1280x720@60Hz' mode with 2 data lanes
+        * requires special fine tuning for DPHY
+        * TIMING config according to the tests.
+        */
+       if (dsim->lanes == 2) {
+               hactive = vmode->hactive;
+               vactive = vmode->vactive;
+
+               if (hactive == 1280 && vactive == 720) {
+                       memset(&mode, 0x0, sizeof(mode));
+                       drm_display_mode_from_videomode(vmode, &mode);
+
+                       if (drm_mode_vrefresh(&mode) == 60)
+                               key.bit_clk >>= 1;
+               }
+       }
+
        match = bsearch(&key, pdata->dphy_timing, pdata->num_dphy_timing,
                        sizeof(struct sec_mipi_dsim_dphy_timing),
                        pdata->dphy_timing_cmp);