MLK-13537 dts: arm: imx7ulp-evk: enable Murata 1DX wifi/bt for evk board

Add Murata 1DX wifi/bt for evk board.

Signed-off-by: Fugang Duan <fugang.duan@nxp.com>

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 339487c..9574bb3 100644 (file)
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -569,7 +569,8 @@ dtb-$(CONFIG_SOC_IMX7D) += \
 dtb-$(CONFIG_SOC_IMX7ULP) += \
        imx7ulp-14x14-arm2.dtb \
        imx7ulp-evk.dtb \
-       imx7ulp-evk-emmc.dtb
+       imx7ulp-evk-emmc.dtb \
+       imx7ulp-evk-lpuart.dtb
 dtb-$(CONFIG_SOC_LS1021A) += \
        ls1021a-qds.dtb \
        ls1021a-twr.dtb

diff --git a/arch/arm/boot/dts/imx7ulp-evk-lpuart.dts b/arch/arm/boot/dts/imx7ulp-evk-lpuart.dts
new file mode 100644 (file)
index 0000000..6c9dba0
--- /dev/null
+++ b/arch/arm/boot/dts/imx7ulp-evk-lpuart.dts
@@ -0,0 +1,17 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "imx7ulp-evk.dts"
+
+&lpi2c7 {
+       status = "disabled";
+};
+
+&lpuart7 { /* Uart test */
+       status = "okay";
+};

diff --git a/arch/arm/boot/dts/imx7ulp-evk.dts b/arch/arm/boot/dts/imx7ulp-evk.dts
index 11763f9..2367ecc 100644 (file)
--- a/arch/arm/boot/dts/imx7ulp-evk.dts
+++ b/arch/arm/boot/dts/imx7ulp-evk.dts
@@ -9,6 +9,7 @@
 /dts-v1/;
 
 #include "imx7ulp.dtsi"
+#include <dt-bindings/gpio/gpio.h>
 
 / {
        model = "NXP i.MX7ULP EVK";
@@ -19,10 +20,33 @@
                stdout-path = &lpuart4;
        };
 
+       bcmdhd_wlan_0: bcmdhd_wlan@0 {
+               compatible = "android,bcmdhd_wlan";
+               wlreg_on-supply = <&wlreg_on>;
+               bcmdhd_fw = "/lib/firmware/bcm/1DX_BCM4343W/fw_bcmdhd.bin";
+               bcmdhd_nv = "/lib/firmware/bcm/1DX_BCM4343W/bcmdhd.1DX.SDIO.cal";
+       };
+
        memory {
                device_type = "memory";
                reg = <0x60000000 0x40000000>;
        };
+
+       regulators {
+               compatible = "simple-bus";
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               wlreg_on: fixedregulator@100 {
+                       compatible = "regulator-fixed";
+                       regulator-min-microvolt = <5000000>;
+                       regulator-max-microvolt = <5000000>;
+                       regulator-name = "wlreg_on";
+                       gpio = <&gpio2 6 GPIO_ACTIVE_HIGH>;
+                       startup-delay-us = <100>;
+                       enable-active-high;
+               };
+       };
 };
 
 &iomuxc1 {
@@ -37,6 +61,32 @@
                        >;
                };
 
+               pinctrl_lpuart4: lpuart4grp {
+                       fsl,pins = <
+                               ULP1_PAD_PTC3__LPUART4_RX       0x400
+                               ULP1_PAD_PTC2__LPUART4_TX       0x400
+                       >;
+               };
+
+               pinctrl_lpuart6: lpuart6grp {
+                       fsl,pins = <
+                               ULP1_PAD_PTE10__LPUART6_TX      0x400
+                               ULP1_PAD_PTE11__LPUART6_RX      0x400
+                               ULP1_PAD_PTE9__LPUART6_RTS_B    0x400
+                               ULP1_PAD_PTE8__LPUART6_CTS_B    0x400
+                               ULP1_PAD_PTE7__PTE7             0x00 /* BT_REG_ON */
+                       >;
+               };
+
+               pinctrl_lpuart7: lpuart7grp {
+                       fsl,pins = <
+                               ULP1_PAD_PTF14__LPUART7_TX      0x400
+                               ULP1_PAD_PTF15__LPUART7_RX      0x400
+                               ULP1_PAD_PTF13__LPUART7_RTS_B   0x400
+                               ULP1_PAD_PTF12__LPUART7_CTS_B   0x400
+                       >;
+               };
+
                pinctrl_usdhc0: usdhc0grp {
                        fsl,pins = <
                                ULP1_PAD_PTD1__SDHC0_CMD        0x843
@@ -62,6 +112,23 @@
                                ULP1_PAD_PTD10__SDHC0_D0        0x843
                        >;
                };
+
+               pinctrl_usdhc1: usdhc1grp {
+                       fsl,pins = <
+                               ULP1_PAD_PTE3__SDHC1_CMD        0x843
+                               ULP1_PAD_PTE2__SDHC1_CLK        0x843
+                               ULP1_PAD_PTE1__SDHC1_D0         0x843
+                               ULP1_PAD_PTE0__SDHC1_D1         0x843
+                               ULP1_PAD_PTE5__SDHC1_D2         0x843
+                               ULP1_PAD_PTE4__SDHC1_D3         0x843
+                       >;
+               };
+
+               pinctrl_wifi: wifigrp {
+                       fsl,pins = <
+                               ULP1_PAD_PTE6__PTE6             0x43 /* WL_REG_ON */
+                       >;
+               };
        };
 };
 
@@ -101,6 +168,24 @@
        };
 };
 
+&lpuart4 { /* console */
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_lpuart4>;
+       status = "okay";
+};
+
+&lpuart6 { /* BT */
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_lpuart6>;
+       status = "okay";
+};
+
+&lpuart7 { /* Uart test */
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_lpuart7>;
+       status = "disabled";
+};
+
 &usdhc0 {
        pinctrl-names = "default", "sleep";
        pinctrl-0 = <&pinctrl_usdhc0>;
@@ -108,3 +193,14 @@
        non-removable;
        status = "okay";
 };
+
+&usdhc1 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_wifi>;
+       non-removable;
+       keep-power-in-suspend;
+       cd-post;
+       pm-ignore-notify;
+       wifi-host;
+       status = "okay";
+};

diff --git a/arch/arm/boot/dts/imx7ulp.dtsi b/arch/arm/boot/dts/imx7ulp.dtsi
index 8ddb169..274c568 100644 (file)
--- a/arch/arm/boot/dts/imx7ulp.dtsi
+++ b/arch/arm/boot/dts/imx7ulp.dtsi
@@ -19,9 +19,12 @@
                gpio1 = &gpio1;
                gpio2 = &gpio2;
                gpio3 = &gpio3;
+               mmc0 = &usdhc0;
+               mmc1 = &usdhc1;
                serial0 = &lpuart4;
-               serial1 = &lpuart6;
-               serial2 = &lpuart5;
+               serial1 = &lpuart5;
+               serial2 = &lpuart6;
+               serial3 = &lpuart7;
                usbphy0 = &usbphy1;
        };
 
@@ -258,6 +261,7 @@
                        assigned-clocks = <&clks IMX7ULP_CLK_LPUART4>;
                        assigned-clock-parents = <&clks IMX7ULP_CLK_OSC>;
                        assigned-clock-rates = <24000000>;
+                       status = "disabled";
                };
 
                lpuart5: serial@402E0000 {
@@ -361,8 +365,10 @@
                        clock-names = "ckil", "osc", "sirc",
                                "firc", "upll", "mpll";
                        #clock-cells = <1>;
-                       assigned-clocks = <&clks IMX7ULP_CLK_LPTPM5>;
-                       assigned-clock-parents = <&clks IMX7ULP_CLK_OSC>;
+                       assigned-clocks = <&clks IMX7ULP_CLK_LPTPM5>,
+                                         <&clks IMX7ULP_CLK_USDHC1>;
+                       assigned-clock-parents = <&clks IMX7ULP_CLK_OSC>,
+                                                <&clks IMX7ULP_CLK_NIC1_DIV>;
                };
 
                pcc2: pcc2@403F0000 {
@@ -389,6 +395,30 @@
                reg = <0x40800000 0x800000>;
                ranges;
 
+               lpi2c6: lpi2c6@40A40000 {
+                       compatible = "fsl,imx7ulp-lpi2c";
+                       reg = <0x40A40000 0x10000>;
+                       interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&clks IMX7ULP_CLK_LPI2C6>;
+                       clock-names = "ipg";
+                       assigned-clocks = <&clks IMX7ULP_CLK_LPI2C6>;
+                       assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>;
+                       assigned-clock-rates = <48000000>;
+                       status = "disabled";
+               };
+
+               lpi2c7: lpi2c7@40A50000 {
+                       compatible = "fsl,imx7ulp-lpi2c";
+                       reg = <0x40A50000 0x10000>;
+                       interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&clks IMX7ULP_CLK_LPI2C7>;
+                       clock-names = "ipg";
+                       assigned-clocks = <&clks IMX7ULP_CLK_LPI2C7>;
+                       assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>;
+                       assigned-clock-rates = <48000000>;
+                       status = "disabled";
+               };
+
                lpuart6: serial@40A60000 {
                        compatible = "fsl,imx7ulp-lpuart";
                        reg = <0x40A60000 0x1000>;
@@ -403,6 +433,20 @@
                        status = "disabled";
                };
 
+               lpuart7: serial@40A70000 {
+                       compatible = "fsl,imx7ulp-lpuart";
+                       reg = <0x40A70000 0x1000>;
+                       interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&clks IMX7ULP_CLK_LPUART7>;
+                       clock-names = "ipg";
+                       assigned-clocks = <&clks IMX7ULP_CLK_LPUART7>;
+                       assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>;
+                       assigned-clock-rates = <50000000>;
+                       dmas = <&edma0 0 24>, <&edma0 0 23>;
+                       dma-names = "tx","rx";
+                       status = "disabled";
+               };
+
                lcdif: lcdif@40AA0000 {
                        compatible = "fsl,imx7ulp-lcdif";
                        reg = <0x40aa0000 0x10000>;