MLK-15144 ARM64: dts: freescale: imx8mq: add enet support

Add enet support for imx8mq evk board.

Signed-off-by: Fugang Duan <fugang.duan@nxp.com>

diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk.dts b/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk.dts
index be6fc20..63a3357 100644 (file)
--- a/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk.dts
@@ -34,6 +34,24 @@
        pinctrl-names = "default";
 
        imx8mq-evk {
+               pinctrl_fec1: fec1grp {
+                       fsl,pins = <
+                               MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC         0x3
+                               MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO       0x23
+                               MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3   0x1f
+                               MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2   0x1f
+                               MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1   0x1f
+                               MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0   0x1f
+                               MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC   0x1f
+                               MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3   0x1f
+                               MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2   0x1f
+                               MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1   0x1f
+                               MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0   0x1f
+                               MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC   0x1f
+                               MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL     0x1f
+                               MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL     0x1f
+                       >;
+               };
 
                pinctrl_uart1: uart1grp {
                        fsl,pins = <
@@ -56,6 +74,26 @@
        };
 };
 
+&fec1 {
+       pinctrl-names = "default";
+       inctrl-0 = <&pinctrl_fec1>;
+       phy-mode = "rgmii";
+       phy-handle = <&ethphy0>;
+       fsl,ar8031-phy-fixup;
+       fsl,magic-packet;
+       status = "okay";
+
+       mdio {
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               ethphy0: ethernet-phy@0 {
+                       compatible = "ethernet-phy-ieee802.3-c22";
+                       reg = <0>;
+               };
+       };
+};
+
 &uart1 {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_uart1>;

diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8mq.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8mq.dtsi
index 55f6f65..a9aaffd 100755 (executable)
--- a/arch/arm64/boot/dts/freescale/fsl-imx8mq.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-imx8mq.dtsi
@@ -26,6 +26,7 @@
        #size-cells = <2>;
 
        aliases {
+               ethernet0 = &fec1;
                serial0 = &uart1;
                serial1 = &uart2;
                serial2 = &uart3;
@@ -442,6 +443,32 @@
                status = "okay";
        };
 
+       fec1: ethernet@30be0000 {
+               compatible = "fsl,imx8qm-fec", "fsl,imx6sx-fec";
+               reg = <0x0 0x30be0000 0x0 0x10000>;
+               interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
+                       <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
+                       <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&clk IMX8MQ_CLK_ENET1_ROOT>,
+                       <&clk IMX8MQ_CLK_ENET1_ROOT>,
+                       <&clk IMX8MQ_CLK_ENET_TIMER_DIV>,
+                       <&clk IMX8MQ_CLK_ENET_REF_DIV>,
+                       <&clk IMX8MQ_CLK_ENET_PHY_REF_DIV>;
+               clock-names = "ipg", "ahb", "ptp",
+                       "enet_clk_ref", "enet_out";
+               assigned-clocks = <&clk IMX8MQ_CLK_ENET_AXI_SRC>,
+                                 <&clk IMX8MQ_CLK_ENET_TIMER_SRC>,
+                                 <&clk IMX8MQ_CLK_ENET_REF_SRC>;
+               assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_266M>,
+                                        <&clk IMX8MQ_SYS2_PLL_100M>,
+                                        <&clk IMX8MQ_SYS2_PLL_125M>;
+               stop-mode = <&gpr 0x10 3>;
+               fsl,num-tx-queues=<3>;
+               fsl,num-rx-queues=<3>;
+               fsl,wakeup_irq = <2>;
+               status = "disabled";
+       };
+
        gpu: gpu@38000000 {
                compatible = "fsl,imx8mq-gpu", "fsl,imx6q-gpu";
                reg = <0x0 0x38000000 0 0x40000>, <0x0 0x60000000 0x0 0x14000000>, <0x0 0x0 0x0 0x2000000>;