u32 cnr;
};
+struct dbg_monitor_regs {
+ u32 ctrl[4]; /* Control */
+ u32 master_en[4]; /* Master enable */
+ u32 irq[4]; /* IRQ */
+ u32 trap_addr_low[4]; /* Trap address low */
+ u32 trap_addr_high[4]; /* Trap address high */
+ u32 trap_id[4]; /* Trap ID */
+ u32 snvs_addr[4]; /* SNVS address */
+ u32 snvs_data[4]; /* SNVS data */
+ u32 snvs_info[4]; /* SNVS info */
+ u32 version[4]; /* Version */
+};
+
/*
* If ROM fail back to USB recover mode, USBPH0_PWD will be clear to use USB
* If boot from the other mode, USB0_PWD will keep reset value
process. With this tool is possible to authenticate the
chip to the OEM's server.
+config DBG_MONITOR
+ bool "Enable the AXI debug monitor"
+ depends on ARCH_MX6 || ARCH_MX7
+ help
+ This option enables the debug monitor which prints out last
+ failed AXI access info when system reboot is caused by AXI
+ access failure.
+
config NXP_BOARD_REVISION
bool "Read NXP board revision from fuses"
depends on ARCH_MX6 || ARCH_MX7
{
u32 cpurev;
__maybe_unused u32 max_freq;
+#if defined(CONFIG_DBG_MONITOR)
+ struct dbg_monitor_regs *dbg =
+ (struct dbg_monitor_regs *)DEBUG_MONITOR_BASE_ADDR;
+#endif
cpurev = get_cpu_rev();
puts("\n");
#endif
+#if defined(CONFIG_DBG_MONITOR)
+ if (readl(&dbg->snvs_addr))
+ printf("DBG snvs regs addr 0x%x, data 0x%x, info 0x%x\n",
+ readl(&dbg->snvs_addr),
+ readl(&dbg->snvs_data),
+ readl(&dbg->snvs_info));
+#endif
+
printf("Reset cause: %s\n", get_reset_cause());
return 0;
}
#include "mx6_common.h"
+#define CONFIG_DBG_MONITOR
+
/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN (3 * SZ_1M)
#include "mx6_common.h"
+#define CONFIG_DBG_MONITOR
+
#ifdef CONFIG_SPL
#include "imx6_spl.h"
#endif