clock-names = "ipg";
};
+ dcss: dcss@32e00000 {
+ compatible = "fsl,imx8mq-dcss";
+ reg = <0x0 0x32e00000 0x0 0x25000>,
+ <0x0 0x32e2f000 0x0 0x1000>; /* blk_ctl registers */
+ clocks = <&clk IMX8MQ_CLK_DISP_AXI_ROOT>,
+ <&clk IMX8MQ_CLK_DISP_APB_ROOT>,
+ <&clk IMX8MQ_CLK_DISP_RTRM_ROOT>,
+ <&clk IMX8MQ_CLK_DISP_DTRC_DIV>,
+ <&clk IMX8MQ_CLK_DC_PIXEL_DIV>;
+ clock-names = "axi", "apb", "rtram", "dtrc", "pix";
+ assigned-clocks = <&clk IMX8MQ_CLK_DC_PIXEL_SRC>;
+ assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>;
+ assigned-clock-rates = <594000000>;
+ interrupt-parent = <&irqsteer_dcss>;
+ interrupts = <3 IRQ_TYPE_LEVEL_HIGH>, /* dpr1 */
+ <4 IRQ_TYPE_LEVEL_HIGH>, /* dpr2 */
+ <5 IRQ_TYPE_LEVEL_HIGH>, /* dpr3 */
+ <6 IRQ_TYPE_LEVEL_HIGH>, /* ctx_ld */
+ <7 IRQ_TYPE_LEVEL_HIGH>, /* rd_src */
+ <15 IRQ_TYPE_LEVEL_HIGH>, /* dec400d_1 */
+ <16 IRQ_TYPE_LEVEL_HIGH>, /* dtrc_2 */
+ <17 IRQ_TYPE_LEVEL_HIGH>, /* dtrc_3 */
+ <18 IRQ_TYPE_LEVEL_HIGH>, /* lut_ld */
+ <19 IRQ_TYPE_LEVEL_HIGH>; /* wr_scl */
+ disp-mode = <16>; /* <default mode: #16>
+ * #16: 1920x1080p@60Hz 16:9
+ */
+ status = "disabled";
+ };
+
lcdif: lcdif@30320000 {
compatible = "fsl,imx8mq-lcdif", "fsl,imx28-lcdif";
reg = <0x0 0x30320000 0x0 0x10000>;