MLK-11401-1 ARM: imx: correct mipi PGC power up/down flow

For SW power up/down mipi phy in GPC, below flow should
be executed:

1. map mipi phy to A7 domain;
2. enable mipi phy PGC bit if it is a disable operation;
3. do software power up/down request in GPC;
4. wait for the software request bit clear.

Previous flow is incorrect, as it miss #4 step, correct it.

Signed-off-by: Anson Huang <b20788@freescale.com>
(cherry picked from commit 707ed61de83e7cc1c7d7b15cc8a1c00bea0bc8d1)

Conflicts:
	arch/arm/mach-imx/gpcv2.c

diff --git a/arch/arm/mach-imx/gpcv2.c b/arch/arm/mach-imx/gpcv2.c
index 1d91852..69b8394 100644 (file)
--- a/arch/arm/mach-imx/gpcv2.c
+++ b/arch/arm/mach-imx/gpcv2.c
@@ -584,28 +584,32 @@ static int imx_mipi_regulator_notify(struct notifier_block *nb,
 {
        u32 val = 0;
 
+       val = readl_relaxed(gpc_base + GPC_PGC_CPU_MAPPING);
+       writel_relaxed(val | BIT(2), gpc_base + GPC_PGC_CPU_MAPPING);
+
        switch (event) {
        case REGULATOR_EVENT_PRE_DO_ENABLE:
-               val = readl_relaxed(gpc_base + GPC_PGC_CPU_MAPPING);
-               writel_relaxed(val | BIT(2), gpc_base + GPC_PGC_CPU_MAPPING);
-
                val = readl_relaxed(gpc_base + GPC_PU_PGC_SW_PUP_REQ);
                writel_relaxed(val | BIT(0), gpc_base + GPC_PU_PGC_SW_PUP_REQ);
+               while (readl_relaxed(gpc_base + GPC_PU_PGC_SW_PUP_REQ) & BIT(0))
+                       ;
                break;
        case REGULATOR_EVENT_PRE_DO_DISABLE:
+               /* only disable phy need to set PGC bit, enable does NOT need */
+               imx_gpcv2_set_m_core_pgc(true, GPC_PGC_MIPI_PHY);
                val = readl_relaxed(gpc_base + GPC_PU_PGC_SW_PDN_REQ);
                writel_relaxed(val | BIT(0), gpc_base + GPC_PU_PGC_SW_PDN_REQ);
-
-               val = readl_relaxed(gpc_base + GPC_PGC_MIPI_PHY);
-               writel_relaxed(val | BIT(0), gpc_base + GPC_PGC_MIPI_PHY);
-
-               val = readl_relaxed(gpc_base + GPC_PGC_CPU_MAPPING);
-               writel_relaxed(val & ~BIT(2), gpc_base + GPC_PGC_CPU_MAPPING);
+               while (readl_relaxed(gpc_base + GPC_PU_PGC_SW_PDN_REQ) & BIT(0))
+                       ;
+               imx_gpcv2_set_m_core_pgc(false, GPC_PGC_MIPI_PHY);
                break;
        default:
                break;
        }
 
+       val = readl_relaxed(gpc_base + GPC_PGC_CPU_MAPPING);
+       writel_relaxed(val & ~BIT(2), gpc_base + GPC_PGC_CPU_MAPPING);
+
        return NOTIFY_OK;
 }