MLK-16738: ARM64: dts: qxp-lpddr4-arm2: amix: move SAIs MCLKs to AUD_PLL1

Move AMIX SAIs MCLKs to AUD_PLL1 and double the frequency
in order to support 64k rate.

Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
Reviewed-by: Frank Li <frank.li@nxp.com>

diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-lpddr4-arm2.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-lpddr4-arm2.dts
index 3dc9afc..15e64f3 100644 (file)
--- a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-lpddr4-arm2.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-lpddr4-arm2.dts
@@ -132,12 +132,12 @@
 
 &sai4 {
        assigned-clocks = <&clk IMX8QXP_ACM_SAI4_MCLK_SEL>,
-                       <&clk IMX8QXP_AUD_PLL0_DIV>,
-                       <&clk IMX8QXP_AUD_ACM_AUD_PLL_CLK0_DIV>,
-                       <&clk IMX8QXP_AUD_ACM_AUD_REC_CLK0_DIV>,
+                       <&clk IMX8QXP_AUD_PLL1_DIV>,
+                       <&clk IMX8QXP_AUD_ACM_AUD_PLL_CLK1_DIV>,
+                       <&clk IMX8QXP_AUD_ACM_AUD_REC_CLK1_DIV>,
                        <&clk IMX8QXP_AUD_SAI_4_MCLK>;
-       assigned-clock-parents = <&clk IMX8QXP_AUD_ACM_AUD_PLL_CLK0_CLK>;
-       assigned-clock-rates = <0>, <786432000>, <49152000>, <24576000>, <49152000>;
+       assigned-clock-parents = <&clk IMX8QXP_AUD_ACM_AUD_PLL_CLK1_CLK>;
+       assigned-clock-rates = <0>, <786432000>, <98304000>, <24576000>, <98304000>;
        fsl,sai-asynchronous;
        fsl,txm-rxs;
        status = "okay";
@@ -145,12 +145,12 @@
 
 &sai5 {
        assigned-clocks = <&clk IMX8QXP_ACM_SAI5_MCLK_SEL>,
-                       <&clk IMX8QXP_AUD_PLL0_DIV>,
-                       <&clk IMX8QXP_AUD_ACM_AUD_PLL_CLK0_DIV>,
-                       <&clk IMX8QXP_AUD_ACM_AUD_REC_CLK0_DIV>,
+                       <&clk IMX8QXP_AUD_PLL1_DIV>,
+                       <&clk IMX8QXP_AUD_ACM_AUD_PLL_CLK1_DIV>,
+                       <&clk IMX8QXP_AUD_ACM_AUD_REC_CLK1_DIV>,
                        <&clk IMX8QXP_AUD_SAI_5_MCLK>;
-       assigned-clock-parents = <&clk IMX8QXP_AUD_ACM_AUD_PLL_CLK0_CLK>;
-       assigned-clock-rates = <0>, <786432000>, <49152000>, <24576000>, <49152000>;
+       assigned-clock-parents = <&clk IMX8QXP_AUD_ACM_AUD_PLL_CLK1_CLK>;
+       assigned-clock-rates = <0>, <786432000>, <98304000>, <24576000>, <98304000>;
        fsl,sai-asynchronous;
        fsl,txm-rxs;
        status = "okay";