/*
* Copyright 2013-2015 Freescale Semiconductor, Inc.
+ * Copyright 2018 NXP
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
clocks = <&clks IMX6QDL_CLK_OCRAM>;
};
+ ocram_optee: sram@00918000 {
+ compatible = "fsl,optee-lpm-sram";
+ reg = <0x00918000 0x8000>;
+ overw_reg = <&ocram 0x00905000 0x13000>;
+ };
+
aips1: aips-bus@02000000 {
iomuxc: iomuxc@020e0000 {
compatible = "fsl,imx6dl-iomuxc";
/*
* Copyright 2013-2015 Freescale Semiconductor, Inc.
+ * Copyright 2018 NXP
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
clocks = <&clks IMX6QDL_CLK_OCRAM>;
};
+ ocram_optee: sram@00938000 {
+ compatible = "fsl,optee-lpm-sram";
+ reg = <0x00938000 0x8000>;
+ overw_reg = <&ocram 0x00905000 0x33000>;
+ };
+
aips-bus@02000000 { /* AIPS1 */
spba-bus@02000000 {
ecspi5: ecspi@02018000 {
/*
* Copyright 2013-2016 Freescale Semiconductor, Inc.
+ * Copyright 2018 NXP
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
clocks = <&clks IMX6SL_CLK_OCRAM>;
};
+ ocram_optee: sram@00918000 {
+ compatible = "fsl,optee-lpm-sram";
+ reg = <0x00918000 0x8000>;
+ overw_reg = <&ocram 0x00905000 0x13000>;
+ };
+
L2: l2-cache@00a02000 {
compatible = "arm,pl310-cache";
reg = <0x00a02000 0x1000>;
/*
* Copyright 2016 Freescale Semiconductor, Inc.
- * Copyright 2017 NXP.
+ * Copyright 2017-2018 NXP
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
reg = <0x00905000 0x1B000>;
};
+ ocram_optee: sram@00918000 {
+ compatible = "fsl,optee-lpm-sram";
+ reg = <0x00918000 0x8000>;
+ overw_reg = <&ocram 0x00905000 0x13000>;
+ };
+
L2: l2-cache@00a02000 {
compatible = "arm,pl310-cache";
reg = <0x00a02000 0x1000>;
<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SLL_CLK_DCP>;
clock-names = "dcp";
- };
+ };
};
aips2: aips-bus@02100000 {
/*
* Copyright 2014-2016 Freescale Semiconductor, Inc.
+ * Copyright 2018 NXP
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
clocks = <&clks IMX6SX_CLK_OCRAM>;
};
+ ocram_optee {
+ compatible = "fsl,optee-lpm-sram";
+ reg = <0x008f8000 0x4000>;
+ overw_reg = <&ocrams_ddr 0x00904000 0x1000>,
+ <&ocram 0x00905000 0x1b000>,
+ <&ocrams 0x00900000 0x4000>;
+ overw_clock = <&ocrams &clks IMX6SX_CLK_OCRAM>;
+ };
+
L2: l2-cache@00a02000 {
compatible = "arm,pl310-cache";
reg = <0x00a02000 0x1000>;
/*
* Copyright 2015-2016 Freescale Semiconductor, Inc.
- * Copyright 2017 NXP.
+ * Copyright 2017-2018 NXP
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
reg = <0x00905000 0x1B000>;
};
+ ocram_optee: sram@00918000 {
+ compatible = "fsl,optee-lpm-sram";
+ reg = <0x00918000 0x8000>;
+ overw_reg = <&ocram 0x00905000 0x13000>;
+ };
+
dma_apbh: dma-apbh@01804000 {
compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
reg = <0x01804000 0x2000>;
/*
* Copyright 2015-2016 Freescale Semiconductor, Inc.
- * Copyright 2017 NXP.
+ * Copyright 2017-2018 NXP
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
reg = <0x00905000 0x1B000>;
};
+ ocram_optee: sram@00918000 {
+ compatible = "fsl,optee-lpm-sram";
+ reg = <0x00918000 0x8000>;
+ overw_reg = <&ocram 0x00905000 0x13000>;
+ };
+
dma_apbh: dma-apbh@01804000 {
compatible = "fsl,imx6ul-dma-apbh", "fsl,imx28-dma-apbh";
reg = <0x01804000 0x2000>;
/*
* Copyright 2015-2016 Freescale Semiconductor, Inc.
* Copyright 2016 Toradex AG
- * Copyright 2017 NXP.
+ * Copyright 2017-2018 NXP
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
clocks = <&clks IMX7D_OCRAM_CLK>;
};
+ ocram_optee {
+ compatible = "fsl,optee-lpm-sram";
+ reg = <0x00180000 0x8000>;
+ overw_reg = <&ocrams_ddr 0x00904000 0x1000>,
+ <&ocram 0x00905000 0x1b000>,
+ <&ocrams 0x00900000 0x4000>;
+ overw_clock = <&ocrams &clks IMX7D_OCRAM_CLK>;
+ };
+
dma_apbh: dma-apbh@33000000 {
compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh";
reg = <0x33000000 0x2000>;