drm/nouveau/gr/gf100-: virtualise init_tex_hww_esr
authorBen Skeggs <bskeggs@redhat.com>
Tue, 8 May 2018 10:39:46 +0000 (20:39 +1000)
committerBen Skeggs <bskeggs@redhat.com>
Fri, 18 May 2018 05:01:23 +0000 (15:01 +1000)
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
17 files changed:
drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c
drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.h
drivers/gpu/drm/nouveau/nvkm/engine/gr/gf104.c
drivers/gpu/drm/nouveau/nvkm/engine/gr/gf108.c
drivers/gpu/drm/nouveau/nvkm/engine/gr/gf110.c
drivers/gpu/drm/nouveau/nvkm/engine/gr/gf117.c
drivers/gpu/drm/nouveau/nvkm/engine/gr/gf119.c
drivers/gpu/drm/nouveau/nvkm/engine/gr/gk104.c
drivers/gpu/drm/nouveau/nvkm/engine/gr/gk110.c
drivers/gpu/drm/nouveau/nvkm/engine/gr/gk110b.c
drivers/gpu/drm/nouveau/nvkm/engine/gr/gk208.c
drivers/gpu/drm/nouveau/nvkm/engine/gr/gm107.c
drivers/gpu/drm/nouveau/nvkm/engine/gr/gm200.c
drivers/gpu/drm/nouveau/nvkm/engine/gr/gp100.c
drivers/gpu/drm/nouveau/nvkm/engine/gr/gp102.c
drivers/gpu/drm/nouveau/nvkm/engine/gr/gp107.c
drivers/gpu/drm/nouveau/nvkm/engine/gr/gp10b.c

index 7764425..25f64ec 100644 (file)
@@ -1914,6 +1914,13 @@ gf100_gr_new_(const struct gf100_gr_func *func, struct nvkm_device *device,
        return 0;
 }
 
+void
+gf100_gr_init_tex_hww_esr(struct gf100_gr *gr, int tpc, int gpc)
+{
+       struct nvkm_device *device = gr->base.engine.subdev.device;
+       nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x224), 0xc0000000);
+}
+
 void
 gf100_gr_init_419eb4(struct gf100_gr *gr)
 {
@@ -2082,7 +2089,8 @@ gf100_gr_init(struct gf100_gr *gr)
                for (tpc = 0; tpc < gr->tpc_nr[gpc]; tpc++) {
                        nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x508), 0xffffffff);
                        nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x50c), 0xffffffff);
-                       nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x224), 0xc0000000);
+                       if (gr->func->init_tex_hww_esr)
+                               gr->func->init_tex_hww_esr(gr, gpc, tpc);
                        nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x084), 0xc0000000);
                        nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x644), 0x001ffffe);
                        nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x64c), 0x0000000f);
@@ -2143,6 +2151,7 @@ gf100_gr = {
        .init_40601c = gf100_gr_init_40601c,
        .init_419cc0 = gf100_gr_init_419cc0,
        .init_419eb4 = gf100_gr_init_419eb4,
+       .init_tex_hww_esr = gf100_gr_init_tex_hww_esr,
        .mmio = gf100_gr_pack_mmio,
        .fecs.ucode = &gf100_gr_fecs_ucode,
        .gpccs.ucode = &gf100_gr_gpccs_ucode,
index e328957..0bbe11d 100644 (file)
@@ -138,6 +138,7 @@ struct gf100_gr_func {
        void (*init_419eb4)(struct gf100_gr *);
        void (*init_419c9c)(struct gf100_gr *);
        void (*init_ppc_exceptions)(struct gf100_gr *);
+       void (*init_tex_hww_esr)(struct gf100_gr *, int gpc, int tpc);
        void (*set_hww_esr_report_mask)(struct gf100_gr *);
        const struct gf100_gr_pack *mmio;
        struct {
@@ -162,6 +163,7 @@ void gf100_gr_init_fecs_exceptions(struct gf100_gr *);
 void gf100_gr_init_40601c(struct gf100_gr *);
 void gf100_gr_init_419cc0(struct gf100_gr *);
 void gf100_gr_init_419eb4(struct gf100_gr *);
+void gf100_gr_init_tex_hww_esr(struct gf100_gr *, int, int);
 
 void gf117_gr_init_zcull(struct gf100_gr *);
 
index 59d4dac..ff03f13 100644 (file)
@@ -123,6 +123,7 @@ gf104_gr = {
        .init_40601c = gf100_gr_init_40601c,
        .init_419cc0 = gf100_gr_init_419cc0,
        .init_419eb4 = gf100_gr_init_419eb4,
+       .init_tex_hww_esr = gf100_gr_init_tex_hww_esr,
        .mmio = gf104_gr_pack_mmio,
        .fecs.ucode = &gf100_gr_fecs_ucode,
        .gpccs.ucode = &gf100_gr_gpccs_ucode,
index 73cb23a..ce60f5a 100644 (file)
@@ -121,6 +121,7 @@ gf108_gr = {
        .init_40601c = gf100_gr_init_40601c,
        .init_419cc0 = gf100_gr_init_419cc0,
        .init_419eb4 = gf100_gr_init_419eb4,
+       .init_tex_hww_esr = gf100_gr_init_tex_hww_esr,
        .mmio = gf108_gr_pack_mmio,
        .fecs.ucode = &gf100_gr_fecs_ucode,
        .gpccs.ucode = &gf100_gr_gpccs_ucode,
index 1d7188e..4c21cbe 100644 (file)
@@ -95,6 +95,7 @@ gf110_gr = {
        .init_40601c = gf100_gr_init_40601c,
        .init_419cc0 = gf100_gr_init_419cc0,
        .init_419eb4 = gf100_gr_init_419eb4,
+       .init_tex_hww_esr = gf100_gr_init_tex_hww_esr,
        .mmio = gf110_gr_pack_mmio,
        .fecs.ucode = &gf100_gr_fecs_ucode,
        .gpccs.ucode = &gf100_gr_gpccs_ucode,
index 3465567..10340e9 100644 (file)
@@ -159,6 +159,7 @@ gf117_gr = {
        .init_40601c = gf100_gr_init_40601c,
        .init_419cc0 = gf100_gr_init_419cc0,
        .init_419eb4 = gf100_gr_init_419eb4,
+       .init_tex_hww_esr = gf100_gr_init_tex_hww_esr,
        .mmio = gf117_gr_pack_mmio,
        .fecs.ucode = &gf117_gr_fecs_ucode,
        .gpccs.ucode = &gf117_gr_gpccs_ucode,
index 28c00cb..5147c59 100644 (file)
@@ -186,6 +186,7 @@ gf119_gr = {
        .init_40601c = gf100_gr_init_40601c,
        .init_419cc0 = gf100_gr_init_419cc0,
        .init_419eb4 = gf100_gr_init_419eb4,
+       .init_tex_hww_esr = gf100_gr_init_tex_hww_esr,
        .mmio = gf119_gr_pack_mmio,
        .fecs.ucode = &gf100_gr_fecs_ucode,
        .gpccs.ucode = &gf100_gr_gpccs_ucode,
index 775b474..1805196 100644 (file)
@@ -473,7 +473,7 @@ gk104_gr_init(struct gf100_gr *gr)
                for (tpc = 0; tpc < gr->tpc_nr[gpc]; tpc++) {
                        nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x508), 0xffffffff);
                        nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x50c), 0xffffffff);
-                       nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x224), 0xc0000000);
+                       gr->func->init_tex_hww_esr(gr, gpc, tpc);
                        nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x084), 0xc0000000);
                        nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x644), 0x001ffffe);
                        nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x64c), 0x0000000f);
@@ -536,6 +536,7 @@ gk104_gr = {
        .init_419cc0 = gf100_gr_init_419cc0,
        .init_419eb4 = gf100_gr_init_419eb4,
        .init_ppc_exceptions = gk104_gr_init_ppc_exceptions,
+       .init_tex_hww_esr = gf100_gr_init_tex_hww_esr,
        .mmio = gk104_gr_pack_mmio,
        .fecs.ucode = &gk104_gr_fecs_ucode,
        .gpccs.ucode = &gk104_gr_gpccs_ucode,
index daaa449..f4c73a9 100644 (file)
@@ -361,6 +361,7 @@ gk110_gr = {
        .init_419cc0 = gf100_gr_init_419cc0,
        .init_419eb4 = gk110_gr_init_419eb4,
        .init_ppc_exceptions = gk104_gr_init_ppc_exceptions,
+       .init_tex_hww_esr = gf100_gr_init_tex_hww_esr,
        .mmio = gk110_gr_pack_mmio,
        .fecs.ucode = &gk110_gr_fecs_ucode,
        .gpccs.ucode = &gk110_gr_gpccs_ucode,
index ee56b00..b585ab2 100644 (file)
@@ -113,6 +113,7 @@ gk110b_gr = {
        .init_419cc0 = gf100_gr_init_419cc0,
        .init_419eb4 = gk110_gr_init_419eb4,
        .init_ppc_exceptions = gk104_gr_init_ppc_exceptions,
+       .init_tex_hww_esr = gf100_gr_init_tex_hww_esr,
        .mmio = gk110b_gr_pack_mmio,
        .fecs.ucode = &gk110_gr_fecs_ucode,
        .gpccs.ucode = &gk110_gr_gpccs_ucode,
index 1e214d9..7d1f585 100644 (file)
@@ -171,6 +171,7 @@ gk208_gr = {
        .init_sked_hww_esr = gk104_gr_init_sked_hww_esr,
        .init_419cc0 = gf100_gr_init_419cc0,
        .init_ppc_exceptions = gk104_gr_init_ppc_exceptions,
+       .init_tex_hww_esr = gf100_gr_init_tex_hww_esr,
        .mmio = gk208_gr_pack_mmio,
        .fecs.ucode = &gk208_gr_fecs_ucode,
        .gpccs.ucode = &gk208_gr_gpccs_ucode,
index df668b9..8ee7723 100644 (file)
@@ -393,7 +393,7 @@ gm107_gr_init(struct gf100_gr *gr)
                for (tpc = 0; tpc < gr->tpc_nr[gpc]; tpc++) {
                        nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x508), 0xffffffff);
                        nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x50c), 0xffffffff);
-                       nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x224), 0xc0000000);
+                       gr->func->init_tex_hww_esr(gr, gpc, tpc);
                        nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x084), 0xc0000000);
                        nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x430), 0xc0000000);
                        nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x644), 0x00dffffe);
@@ -458,6 +458,7 @@ gm107_gr = {
        .init_sked_hww_esr = gk104_gr_init_sked_hww_esr,
        .init_419cc0 = gf100_gr_init_419cc0,
        .init_ppc_exceptions = gk104_gr_init_ppc_exceptions,
+       .init_tex_hww_esr = gf100_gr_init_tex_hww_esr,
        .mmio = gm107_gr_pack_mmio,
        .fecs.ucode = &gm107_gr_fecs_ucode,
        .gpccs.ucode = &gm107_gr_gpccs_ucode,
index 9f8171a..0d02009 100644 (file)
@@ -121,7 +121,7 @@ gm200_gr_init(struct gf100_gr *gr)
                for (tpc = 0; tpc < gr->tpc_nr[gpc]; tpc++) {
                        nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x508), 0xffffffff);
                        nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x50c), 0xffffffff);
-                       nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x224), 0xc0000000);
+                       gr->func->init_tex_hww_esr(gr, gpc, tpc);
                        nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x084), 0xc0000000);
                        nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x430), 0xc0000000);
                        nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x644), 0x00dffffe);
@@ -204,6 +204,7 @@ gm200_gr = {
        .init_sked_hww_esr = gk104_gr_init_sked_hww_esr,
        .init_419cc0 = gf100_gr_init_419cc0,
        .init_ppc_exceptions = gk104_gr_init_ppc_exceptions,
+       .init_tex_hww_esr = gf100_gr_init_tex_hww_esr,
        .rops = gm200_gr_rops,
        .ppc_nr = 2,
        .grctx = &gm200_grctx,
index 3fcbe1f..c798608 100644 (file)
@@ -101,7 +101,7 @@ gp100_gr_init(struct gf100_gr *gr)
                for (tpc = 0; tpc < gr->tpc_nr[gpc]; tpc++) {
                        nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x508), 0xffffffff);
                        nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x50c), 0xffffffff);
-                       nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x224), 0xc0000000);
+                       gr->func->init_tex_hww_esr(gr, gpc, tpc);
                        nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x084), 0xc0000000);
                        nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x430), 0xc0000000);
                        nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x644), 0x00dffffe);
@@ -144,6 +144,7 @@ gp100_gr = {
        .init_419cc0 = gf100_gr_init_419cc0,
        .init_419c9c = gp100_gr_init_419c9c,
        .init_ppc_exceptions = gk104_gr_init_ppc_exceptions,
+       .init_tex_hww_esr = gf100_gr_init_tex_hww_esr,
        .rops = gm200_gr_rops,
        .ppc_nr = 2,
        .grctx = &gp100_grctx,
index 230e2ee..a7fe2d9 100644 (file)
@@ -54,6 +54,7 @@ gp102_gr = {
        .init_sked_hww_esr = gk104_gr_init_sked_hww_esr,
        .init_419cc0 = gf100_gr_init_419cc0,
        .init_ppc_exceptions = gk104_gr_init_ppc_exceptions,
+       .init_tex_hww_esr = gf100_gr_init_tex_hww_esr,
        .rops = gm200_gr_rops,
        .ppc_nr = 3,
        .grctx = &gp102_grctx,
index 55b7a7e..f085d01 100644 (file)
@@ -40,6 +40,7 @@ gp107_gr = {
        .init_sked_hww_esr = gk104_gr_init_sked_hww_esr,
        .init_419cc0 = gf100_gr_init_419cc0,
        .init_ppc_exceptions = gk104_gr_init_ppc_exceptions,
+       .init_tex_hww_esr = gf100_gr_init_tex_hww_esr,
        .rops = gm200_gr_rops,
        .ppc_nr = 1,
        .grctx = &gp107_grctx,
index b13a48b..9530edc 100644 (file)
@@ -38,6 +38,7 @@ gp10b_gr = {
        .init_sked_hww_esr = gk104_gr_init_sked_hww_esr,
        .init_419cc0 = gf100_gr_init_419cc0,
        .init_ppc_exceptions = gk104_gr_init_ppc_exceptions,
+       .init_tex_hww_esr = gf100_gr_init_tex_hww_esr,
        .rops = gm200_gr_rops,
        .ppc_nr = 1,
        .grctx = &gp102_grctx,