clocks = <&clks IMX6QDL_CLK_OCRAM>;
};
+ ocram_optee: sram@918000 {
+ compatible = "fsl,optee-lpm-sram";
+ reg = <0x918000 0x8000>;
+ overw_reg = <&ocram 0x905000 0x13000>;
+ };
+
gpu: gpu@00130000 {
compatible = "fsl,imx6dl-gpu", "fsl,imx6q-gpu";
reg = <0x00130000 0x4000>, <0x00134000 0x4000>,
clocks = <&clks IMX6QDL_CLK_OCRAM>;
};
+ ocram_optee: sram@00938000 {
+ compatible = "fsl,optee-lpm-sram";
+ reg = <0x00938000 0x8000>;
+ overw_reg = <&ocram 0x00905000 0x33000>;
+ };
+
bus@2000000 { /* AIPS1 */
spba-bus@2000000 {
ecspi5: spi@2018000 {
clocks = <&clks IMX6SX_CLK_OCRAM>;
};
+ ocram_optee {
+ compatible = "fsl,optee-lpm-sram";
+ reg = <0x8f8000 0x4000>;
+ overw_reg = <&ocrams_ddr 0x904000 0x1000>,
+ <&ocram 0x905000 0x1b000>,
+ <&ocrams 0x900000 0x4000>;
+ overw_clock = <&ocrams &clks IMX6SX_CLK_OCRAM>;
+ };
+
intc: interrupt-controller@a01000 {
compatible = "arm,cortex-a9-gic";
#interrupt-cells = <3>;
status = "disabled";
};
+ ocram_optee {
+ compatible = "fsl,optee-lpm-sram";
+ reg = <0x180000 0x8000>;
+ overw_reg = <&ocrams_ddr 0x904000 0x1000>,
+ <&ocram 0x905000 0x1b000>,
+ <&ocrams 0x900000 0x4000>;
+ overw_clock = <&ocrams &clks IMX7D_OCRAM_CLK>;
+ };
+
ocrams_mf: sram-mf@00900000 {
compatible = "fsl,mega-fast-sram";
reg = <0x00900000 0x20000>;