Merge Cadence HDMI API V1.0.36 code.
Signed-off-by: Sandor Yu <Sandor.yu@nxp.com>
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
* OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
- * Copyright 2017 NXP
+ * Copyright 2017-2018 NXP
*
******************************************************************************
*
#include "util.h"
typedef enum {
- AFE_LINK_RATE_1_6 = 0x6,
- AFE_LINK_RATE_2_7 = 0xA,
- AFE_LINK_RATE_5_4 = 0x14,
- AFE_LINK_RATE_8_1 = 0x1A,
+ AFE_LINK_RATE_1_6 = 0x6, /* 1.62 Gb/s */
+ AFE_LINK_RATE_2_1 = 0x8, /* 2.16 Gb/s */
+ AFE_LINK_RATE_2_4 = 0x9, /* 2.43 Gb/s */
+ AFE_LINK_RATE_2_7 = 0xA, /* 2.70 Gb/s */
+ AFE_LINK_RATE_3_2 = 0xC, /* 3.24 Gb/s */
+ AFE_LINK_RATE_4_3 = 0x10, /* 4.32 Gb/s */
+ AFE_LINK_RATE_5_4 = 0x14, /* 5.40 Gb/s */
+ AFE_LINK_RATE_8_1 = 0x1E, /* 8.10 Gb/s */
} ENUM_AFE_LINK_RATE;
+/* Some of the PHY programming sequences
+ * depend on the reference clock frequency.
+ * Variable of this type is used to control
+ * the programming flow. */
+typedef enum {
+ REFCLK_24MHZ,
+ REFCLK_27MHZ
+} REFCLK_FREQ;
+
typedef enum {
CLK_RATIO_1_1,
CLK_RATIO_5_4,
u8 msb;
} reg_field_t;
+u8 AFE_check_rate_supported(ENUM_AFE_LINK_RATE rate);
void Afe_write(state_struct *state, u32 offset, u16 val);
u16 Afe_read(state_struct *state, u32 offset);
void AFE_init(state_struct *state, int num_lanes,
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
* OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
+ * Copyright 2017-2018 NXP
+ *
******************************************************************************
*
* API_DPTX.c
u8 fastLinkTraining,
u8 laneMapping, u8 enchanced)
{
+ /* fifth bit of lanesCount_SSC is used to declare eDP. */
+ state->edp = ((lanesCount_SSC >> 5) & 1);
if (!state->running) {
if (!internal_apb_available(state))
return CDN_BSY;
internal_block_function(&state->mutex, CDN_API_DPTX_Control(state, mode));
}
+CDN_API_STATUS CDN_API_DPTX_EDP_Training(state_struct *state,
+ u8 mode, ENUM_AFE_LINK_RATE linkRate,
+ u8 rateId)
+{
+ if (AFE_check_rate_supported(linkRate) == 0)
+ return CDN_ERROR_NOT_SUPPORTED;
+
+ if (!state->running) {
+ if (!internal_apb_available(state))
+ return CDN_BSY;
+ internal_tx_mkfullmsg(state, MB_MODULE_ID_DP_TX, DPTX_EDP_RATE_TRAINING, 3,
+ 1, mode,
+ 1, (u8)linkRate,
+ 1, rateId);
+ state->bus_type = CDN_BUS_TYPE_APB;
+ return CDN_STARTED;
+ }
+ internal_process_messages(state);
+ return CDN_OK;
+}
+
+CDN_API_STATUS CDN_API_DPTX_EDP_Training_blocking(state_struct *state,
+ u8 mode,
+ ENUM_AFE_LINK_RATE linkRate,
+ u8 rateId)
+{
+ internal_block_function(&state->mutex, CDN_API_DPTX_EDP_Training(state, mode, linkRate, rateId));
+}
+
CDN_API_STATUS CDN_API_DPTX_Write_DPCD(state_struct *state, u32 numOfBytes,
- u32 addr, u8 *buff,
- DPTX_Write_DPCD_response *resp,
- CDN_BUS_TYPE bus_type)
+ u32 addr, u8 *buff,
+ DPTX_Write_DPCD_response *resp,
+ CDN_BUS_TYPE bus_type)
{
CDN_API_STATUS ret;
if (!state->running) {
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
* OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
- * Copyright 2017 NXP
+ * Copyright 2017-2018 NXP
*
******************************************************************************
*
#ifndef _API_DPTX_H_
#define _API_DPTX_H_
-# include "API_General.h"
-# include "vic_table.h"
+#include "API_General.h"
+#include "vic_table.h"
+#include "API_AFE.h"
#define MAX_NUM_OF_EVENTS 4
*/
CDN_API_STATUS CDN_API_DPTX_Control_blocking(state_struct *state, u32 mode);
+/**
+ * \brief Performs Fast Link Training, using LINK_RATE_SET DPCD register.
+ * \param [in] mode - 0 to stop training, 1 to start it, 2 to restart it.
+ * \param [in] linkRate - Link Rate to be used for training.
+ * \param [in] rateId - index of selected Link Rate in DPCd registers.
+ *
+ * Performs Fast Link Training, selecting Link Rate using LINK_RATE_SET DPCD
+ * register, characteristic to Embedded DisplayPort (eDP) v1.4 standard.
+ * If requested link rate is not supported by DPTX, function will return error
+ * code CDN_ERROR_NOT_SUPPORTED, and will take no further action.
+ * rateId is used to select, which Link Rate supported by sink (enumerated in
+ * SUPPORTED_LINK_RATES DPCD registers) is equal to rate requested. This value
+ * will be written to first 3 bits of LINK_RATE_SET DPCD registers. Allowed
+ * range is 0-7. If it is not known beforehand, SUPPORTED_LINK_RATES DPCD
+ * registers may be read by an upper layer, and then used to determine the
+ * correct value to use.
+ */
+CDN_API_STATUS CDN_API_DPTX_EDP_Training(state_struct *state, u8 mode, ENUM_AFE_LINK_RATE linkRate, u8 rateId);
+CDN_API_STATUS CDN_API_DPTX_EDP_Training_blocking(state_struct *state, u8 mode, ENUM_AFE_LINK_RATE linkRate, u8 rateId);
/**
* \brief send DPX_ENABLE_EVENT command
*/
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
* OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
- * Copyright 2017 NXP
+ * Copyright 2017-2018 NXP
*
******************************************************************************
*
#include "apb_cfg.h"
#include "opcodes.h"
#include "general_handler.h"
+#include "util.h"
static u32 alive;
{
internal_block_function(&state->mutex, CDN_API_General_Phy_Test_Access(state, resp));
}
+
+CDN_API_STATUS CDN_API_General_GetHpdState(state_struct *state, u8 *hpd_state)
+{
+ CDN_API_STATUS ret;
+ *hpd_state = 0;
+
+ if (!state->running) {
+ if (!internal_apb_available(state))
+ return CDN_BSY;
+ internal_tx_mkfullmsg(state, MB_MODULE_ID_GENERAL, GENERAL_GET_HPD_STATE, 0);
+ state->bus_type = CDN_BUS_TYPE_APB;
+ state->rxEnable = 1;
+ return CDN_STARTED;
+ }
+
+ internal_process_messages(state);
+ ret = internal_test_rx_head(state, MB_MODULE_ID_GENERAL, GENERAL_GET_HPD_STATE);
+ if (ret != CDN_OK)
+ return ret;
+
+ internal_readmsg(state, 1, 1, hpd_state);
+
+ return CDN_OK;
+}
+
+CDN_API_STATUS CDN_API_General_GetHpdState_blocking(state_struct *state, u8 *hpd_state)
+{
+ internal_block_function(&state->mutex, CDN_API_General_GetHpdState(state, hpd_state));
+}
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
* OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
- * Copyright 2017 NXP
+ * Copyright 2017-2018 NXP
*
******************************************************************************
*
CDN_API_STATUS CDN_API_General_Phy_Test_Access(state_struct *state, u8 *resp);
CDN_API_STATUS CDN_API_General_Phy_Test_Access_blocking(state_struct *state,
u8 *resp);
+CDN_API_STATUS CDN_API_General_GetHpdState(state_struct *state, u8 *hpd_state);
+CDN_API_STATUS CDN_API_General_GetHpdState_blocking(state_struct *state, u8 *hpd_state);
#endif
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
* OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
- * Copyright 2017 NXP
+ * Copyright 2017-2018 NXP
*
******************************************************************************
*
#include "address.h"
#include "source_car.h"
#include "source_vif.h"
+#include "general_handler.h"
#include <soc/imx8/soc.h>
CDN_API_STATUS CDN_API_HDMITX_DDC_READ(state_struct *state,
if (!state->running) {
if (!internal_apb_available(state))
return CDN_BSY;
- internal_tx_mkfullmsg(state, MB_MODULE_ID_HDMI_TX,
- HDMI_TX_HPD_STATUS, 0);
+ internal_tx_mkfullmsg(state, MB_MODULE_ID_GENERAL, GENERAL_GET_HPD_STATE, 0);
state->rxEnable = 1;
state->bus_type = CDN_BUS_TYPE_APB;
return CDN_STARTED;
}
internal_process_messages(state);
ret =
- internal_test_rx_head(state, MB_MODULE_ID_HDMI_TX,
- HDMI_TX_HPD_STATUS);
+ internal_test_rx_head(state, MB_MODULE_ID_GENERAL, GENERAL_GET_HPD_STATE);
if (ret != CDN_OK)
return ret;
internal_readmsg(state, 1, 1, hpd_sts);
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
* OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
- * Copyright 2017 NXP
+ * Copyright 2017-2018 NXP
*
******************************************************************************
*
#define GENERAL_WRITE_REGISTER 0x05
#define GENERAL_WRITE_FIELD 0x06
#define GENERAL_READ_REGISTER 0x07
+#define GENERAL_GET_HPD_STATE 0x11
#define GENERAL_TEST_TRNG_SIMPLE 0xF0
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
* OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
- * Copyright 2017 NXP
+ * Copyright 2017-2018 NXP
*
******************************************************************************
*
#define DPTX_SET_LINK_BREAK_POINT 0x0F
#define DPTX_FORCE_LANES 0x10
#define DPTX_HPD_STATE 0x11
+#define DPTX_EDP_RATE_TRAINING 0x12
#define DPTX_DBG_SET 0xF0
#define DP_TX_OPCODE_READ_I2C_REQUEST 0xA5
#define DP_TX_OPCODE_WRITE_I2C_REQUEST 0xA6
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
* OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
- * Copyright 2017 NXP
+ * Copyright 2017-2018 NXP
*
******************************************************************************
*
CDN_CEC_ERR_RX_FAILED,
/** Operation aborted. */
CDN_CEC_ERR_ABORT,
+ /** All Logical Addresses are in use. */
+ CDN_CEC_ERR_ALL_LA_IN_USE,
} CDN_API_STATUS;
typedef enum {
u8 running;
CDN_BUS_TYPE bus_type;
u32 tmp;
+ u32 edp; /* use eDP */
struct mutex mutex; //mutex may replace running
struct hdp_mem *mem;
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
* OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
- * Copyright 2017 NXP
+ * Copyright 2017-2018 NXP
*
******************************************************************************
*
typedef enum {
RATE_1_6 = 162,
+ RATE_2_1 = 216,
+ RATE_2_4 = 243,
RATE_2_7 = 270,
+ RATE_3_2 = 324,
+ RATE_4_3 = 432,
RATE_5_4 = 540,
RATE_8_1 = 810,
} VIC_SYMBOL_RATE;
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