MLK-17634-16: drm: imx: dcss: make 10-bit formats work with HDR

Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>

diff --git a/drivers/gpu/drm/imx/dcss/dcss-plane.c b/drivers/gpu/drm/imx/dcss/dcss-plane.c
index 0efbd97..a50ad4e 100644 (file)
--- a/drivers/gpu/drm/imx/dcss/dcss-plane.c
+++ b/drivers/gpu/drm/imx/dcss/dcss-plane.c
@@ -384,10 +384,6 @@ static void dcss_plane_atomic_update(struct drm_plane *plane,
                return;
        }
 
-       dcss_dpr_enable(dcss_plane->dcss, dcss_plane->ch_num, false);
-       dcss_scaler_enable(dcss_plane->dcss, dcss_plane->ch_num, false);
-       dcss_dtg_ch_enable(dcss_plane->dcss, dcss_plane->ch_num, false);
-
        disp.x1 = 0;
        disp.y1 = 0;
        disp.x2 = crtc_state->adjusted_mode.hdisplay;
@@ -453,7 +449,7 @@ static void dcss_plane_atomic_update(struct drm_plane *plane,
 
        ipipe_cfg.pixel_format = pixel_format;
        ipipe_cfg.nl = NL_REC709;
-       ipipe_cfg.pr = PR_LIMITED;
+       ipipe_cfg.pr = PR_FULL;
        ipipe_cfg.g = G_REC709;
 
        dcss_crtc_get_opipe_cfg(state->crtc, &opipe_cfg);

diff --git a/drivers/gpu/imx/dcss/dcss-dpr.c b/drivers/gpu/imx/dcss/dcss-dpr.c
index 279f482..19525d2 100644 (file)
--- a/drivers/gpu/imx/dcss/dcss-dpr.c
+++ b/drivers/gpu/imx/dcss/dcss-dpr.c
@@ -240,7 +240,7 @@ static u32 dcss_dpr_x_pix_wide_adjust(struct dcss_dpr_ch *ch, u32 pix_wide,
        pix_in_64byte = pix_in_64byte_map[ch->pix_size][ch->tile];
 
        if (pix_format == DRM_FORMAT_P010)
-               pix_wide *= 10 / 8;
+               pix_wide = pix_wide * 10 / 8;
 
        div_64byte_mod = pix_wide % pix_in_64byte;
        offset = (div_64byte_mod == 0) ? 0 : (pix_in_64byte - div_64byte_mod);
@@ -275,6 +275,9 @@ void dcss_dpr_set_res(struct dcss_soc *dcss, int ch_num, u32 xres, u32 yres,
            pix_format == DRM_FORMAT_P010)
                max_planes = 2;
 
+       if (pix_format == DRM_FORMAT_P010)
+               adj_w = adj_w * 10 / 8;
+
        for (plane = 0; plane < max_planes; plane++) {
                yres = plane == 1 ? yres >> 1 : yres;
 
@@ -282,7 +285,7 @@ void dcss_dpr_set_res(struct dcss_soc *dcss, int ch_num, u32 xres, u32 yres,
                pix_y_high = dcss_dpr_y_pix_high_adjust(ch, yres, pix_format);
 
                /* DTRC may need another width alignment. If it does, use it. */
-               if (pix_x_wide != adj_w)
+               if (pix_x_wide < adj_w)
                        pix_x_wide = adj_w;
 
                if (pix_y_high != adj_h)

diff --git a/drivers/gpu/imx/dcss/dcss-dtrc.c b/drivers/gpu/imx/dcss/dcss-dtrc.c
index 2a9bc48..b19b335 100644 (file)
--- a/drivers/gpu/imx/dcss/dcss-dtrc.c
+++ b/drivers/gpu/imx/dcss/dcss-dtrc.c
@@ -331,6 +331,7 @@ void dcss_dtrc_set_res(struct dcss_soc *dcss, int ch_num, struct drm_rect *src,
        int bank;
        u32 old_xres, old_yres, xres, yres;
        u32 pix_depth;
+       u16 width_align = 0;
 
        if (ch_num == 0)
                return;
@@ -358,10 +359,11 @@ void dcss_dtrc_set_res(struct dcss_soc *dcss, int ch_num, struct drm_rect *src,
 
        /*
         * Image original size is aligned:
-        *   - 128 pixels for width;
+        *   - 128 pixels for width (8-bit) or 256 (10-bit);
         *   - 8 lines for height;
         */
-       if (xres == old_xres && !(xres & 0x7f) &&
+       width_align = ch->pix_format == DRM_FORMAT_P010 ? 0xff : 0x7f;
+       if (xres == old_xres && !(xres & width_align) &&
            yres == old_yres && !(yres & 0xf)) {
                ch->dctl &= ~CROPPING_EN;
                goto exit;
@@ -369,9 +371,9 @@ void dcss_dtrc_set_res(struct dcss_soc *dcss, int ch_num, struct drm_rect *src,
 
        /* align the image size: down align for compressed formats */
        if (ch->format_modifier == DRM_FORMAT_MOD_VSI_G2_TILED_COMPRESSED && src->x1)
-               xres = xres & ~0x7f;
+               xres = xres & ~width_align;
        else
-               xres = (xres - 1 + 0x7f) & ~0x7f;
+               xres = (xres - 1 + width_align) & ~width_align;
 
        if (ch->format_modifier == DRM_FORMAT_MOD_VSI_G2_TILED_COMPRESSED && src->y1)
                yres = yres & ~0xf;

diff --git a/drivers/gpu/imx/dcss/dcss-hdr10.c b/drivers/gpu/imx/dcss/dcss-hdr10.c
index c6032ed..0f09321 100644 (file)
--- a/drivers/gpu/imx/dcss/dcss-hdr10.c
+++ b/drivers/gpu/imx/dcss/dcss-hdr10.c
@@ -598,7 +598,8 @@ static u64 dcss_hdr10_get_desc(struct dcss_hdr10_pipe_cfg *ipipe_cfg,
 {
        u32 ipipe_desc, opipe_desc;
 
-       ipipe_desc = dcss_hdr10_pipe_desc(ipipe_cfg);
+       ipipe_desc = dcss_hdr10_pipe_desc(ipipe_cfg) & (~HDR10_BPC_MASK);
+       ipipe_desc |= 2 << HDR10_BPC_POS;
        opipe_desc = dcss_hdr10_pipe_desc(opipe_cfg);
 
        return (ipipe_desc & 0xFFFF) |
@@ -631,6 +632,11 @@ void dcss_hdr10_setup(struct dcss_soc *dcss, int ch_num,
        u64 desc = dcss_hdr10_get_desc(ipipe_cfg, opipe_cfg);
 
        dcss_hdr10_pipe_setup(dcss, ch_num, desc);
-       dcss_hdr10_pipe_setup(dcss, OPIPE_CH_NO, desc);
+
+       /*
+        * Input pipe configuration doesn't matter for configuring the output
+        * pipe. So, will just mask off the input part of the descriptor.
+        */
+       dcss_hdr10_pipe_setup(dcss, OPIPE_CH_NO, desc | 0xffff);
 }
 EXPORT_SYMBOL(dcss_hdr10_setup);

diff --git a/drivers/gpu/imx/dcss/dcss-scaler.c b/drivers/gpu/imx/dcss/dcss-scaler.c
index 1a28999..43bc276 100644 (file)
--- a/drivers/gpu/imx/dcss/dcss-scaler.c
+++ b/drivers/gpu/imx/dcss/dcss-scaler.c
@@ -617,7 +617,8 @@ void dcss_scaler_setup(struct dcss_soc *dcss, int ch_num, u32 pix_format,
 
                dcss_scaler_yuv_coef_set(dcss, ch_num);
 
-               /* TODO: determine component depth for YUV */
+               if (pix_format == DRM_FORMAT_P010)
+                       pixel_depth = 30;
 
        } else if (dcss_cs == DCSS_COLORSPACE_RGB) {
                dcss_scaler_yuv_enable(dcss, ch_num, false);