MLK-25486 imx8mp: Set MEDIA_AXI_CLK_ROOT to 400Mhz

MEDIA_AXI_CLK_ROOT is 400Mhz for nominal voltage while 500Mhz is
for overdrive voltage.
Since we use OD VDD_SOC voltage for LPDDR4 EVK board, but ND for
DDR4 EVK board. Using 500Mhz will break for DDR4 EVK. So set it to
400Mhz that can work both ND and OD.

Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Jacky Bai <ping.bai@nxp.com>

diff --git a/arch/arm/mach-imx/imx8m/clock_imx8mm.c b/arch/arm/mach-imx/imx8m/clock_imx8mm.c
index 29ec8f2..a97498c 100644 (file)
--- a/arch/arm/mach-imx/imx8m/clock_imx8mm.c
+++ b/arch/arm/mach-imx/imx8m/clock_imx8mm.c
@@ -325,8 +325,8 @@ void enable_display_clk(unsigned char enable)
                /* Set Video PLL to 594Mhz, p = 1, m = 99,  k = 0, s = 2 */
                fracpll_configure(ANATOP_VIDEO_PLL, VIDEO_PLL_RATE);
 
-               /* 500Mhz */
-               clock_set_target_val(MEDIA_AXI_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(1) | CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV2));
+               /* 400Mhz */
+               clock_set_target_val(MEDIA_AXI_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(2) | CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV2));
 
                /* 200Mhz */
                clock_set_target_val(MEDIA_APB_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(2) |CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV4));