MLK-14866-1 dt-bindings: pinctrl: add imx7ulp binding doc

Add i.MX7ULP binding doc. Note i.MX7ULP PIN_FUNC_ID consists of 4
integers as it shares one mux and config register as follows:
<mux_conf_reg input_reg mux_mode input_val>

Also fix the copyright.

Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>

diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx7ulp-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,imx7ulp-pinctrl.txt
new file mode 100644 (file)
index 0000000..541aead
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/fsl,imx7ulp-pinctrl.txt
@@ -0,0 +1,33 @@
+* Freescale i.MX7ULP IOMUX Controller
+
+Please refer to fsl,imx-pinctrl.txt in this directory for common binding part
+and usage.
+
+Required properties:
+- compatible: "fsl,imx7ulp-iomuxc-0" or "fsl,imx7ulp-iomuxc-1"
+- fsl,pins: two integers array, represents a group of pins mux and config
+  setting. The format is fsl,pins = <PIN_FUNC_ID CONFIG>, PIN_FUNC_ID is a
+  pin working on a specific function, CONFIG is the pad setting value like
+  pull-up for this pin. Please refer to imx7ulp datasheet for the valid pad
+  config settings.
+
+NOTE: i.MX7ULP PIN_FUNC_ID consists of 4 integers as it shares one mux and
+config register as follows:
+<mux_conf_reg input_reg mux_mode input_val>
+
+CONFIG bits definition:
+PAD_CTL_OBE                    (1 << 17)
+PAD_CTL_IBE                    (1 << 16)
+PAD_CTL_LK                     (1 << 15)
+PAD_CTL_DSE_HIGH               (1 << 6)
+PAD_CTL_DSE_STD                        (0 << 6)
+PAD_CTL_ODE_OPEN_DRAIN         (1 << 5)
+PAD_CTL_ODE_PUSH_PULL          (0 << 5)
+PAD_CTL_SRE_SLOW               (1 << 2)
+PAD_CTL_SRE_STD                        (0 << 2)
+PAD_CTL_PE_PULL                        (1 << 1)
+PAD_CTL_PS_UP                  (1 << 0)
+PAD_CTL_PS_DOWN                        (0 << 0)
+
+Refer to imx7ulp-pinfunc.h in device tree source folder for all available
+imx7ulp PIN_FUNC_ID.

diff --git a/arch/arm/boot/dts/imx7ulp-pinfunc.h b/arch/arm/boot/dts/imx7ulp-pinfunc.h
index b1b6a71..388345d 100644 (file)
--- a/arch/arm/boot/dts/imx7ulp-pinfunc.h
+++ b/arch/arm/boot/dts/imx7ulp-pinfunc.h
@@ -1,5 +1,6 @@
 /*
- * Copyright 2014 - 2015 Freescale Semiconductor, Inc.
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -12,15 +13,7 @@
 
 /*
  * The pin function ID is a tuple of
- * <mux_conf_reg mux2_reg mux_mode mux2_val>
- *
- * !!! IMPORTANT NOTE !!!
- *
- * There's common mux_reg & conf_reg register for each pad on ULP1 device, so the first
- * two values are defined as same value. Extra non-zero mux2_reg value within the tuple
- * means that there's additional mux2 control register that must be configured to
- * mux2_val accordingly to fetch desired pin functionality on ULP1 device.
- *
+ * <mux_conf_reg input_reg mux_mode input_val>
  */
 
 #define ULP1_PAD_PTA0_LLWU0_P0__CMP0_IN2A                         0x0000 0x0000 0x0 0x0