reg = <0x40250000 0x1000>;
nxp,pwm-number = <6>;
assigned-clocks = <&clks IMX7ULP_CLK_LPTPM4>;
- assigned-clock-parents = <&clks IMX7ULP_CLK_SOSC>;
+ assigned-clock-parents = <&clks IMX7ULP_CLK_SOSC_BUS_CLK>;
clocks = <&clks IMX7ULP_CLK_LPTPM4>;
#pwm-cells = <2>;
};
clocks = <&clks IMX7ULP_CLK_LPIT1>;
assigned-clock-rates = <48000000>;
assigned-clocks = <&clks IMX7ULP_CLK_LPIT1>;
- assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>;
+ assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC_BUS_CLK>;
};
lpi2c4: lpi2c4@402B0000 {
<&clks IMX7ULP_CLK_NIC1_BUS_DIV>;
clock-names = "per", "ipg";
assigned-clocks = <&clks IMX7ULP_CLK_LPI2C4>;
- assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>;
+ assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC_BUS_CLK>;
assigned-clock-rates = <48000000>;
status = "disabled";
};
<&clks IMX7ULP_CLK_NIC1_BUS_DIV>;
clock-names = "per", "ipg";
assigned-clocks = <&clks IMX7ULP_CLK_LPI2C5>;
- assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>;
+ assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC_BUS_CLK>;
assigned-clock-rates = <48000000>;
};
<&clks IMX7ULP_CLK_DUMMY>;
clock-names = "per", "ipg";
assigned-clocks = <&clks IMX7ULP_CLK_LPSPI2>;
- assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>;
+ assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC_BUS_CLK>;
assigned-clock-rates = <48000000>;
status = "disabled";
};
<&clks IMX7ULP_CLK_DUMMY>;
clock-names = "per", "ipg";
assigned-clocks = <&clks IMX7ULP_CLK_LPSPI3>;
- assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>;
+ assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC_BUS_CLK>;
assigned-clock-rates = <48000000>;
status = "disabled";
};
clocks = <&clks IMX7ULP_CLK_LPUART4>;
clock-names = "ipg";
assigned-clocks = <&clks IMX7ULP_CLK_LPUART4>;
- assigned-clock-parents = <&clks IMX7ULP_CLK_SOSC>;
+ assigned-clock-parents = <&clks IMX7ULP_CLK_SOSC_BUS_CLK>;
assigned-clock-rates = <24000000>;
status = "disabled";
};
clocks = <&clks IMX7ULP_CLK_LPUART5>;
clock-names = "ipg";
assigned-clocks = <&clks IMX7ULP_CLK_LPUART5>;
- assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>;
+ assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC_BUS_CLK>;
assigned-clock-rates = <48000000>;
dmas = <&edma0 0 20>, <&edma0 0 19>;
dma-names = "tx","rx";
interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX7ULP_CLK_WDG1>;
assigned-clocks = <&clks IMX7ULP_CLK_WDG1>;
- assigned-clocks-parents = <&clks IMX7ULP_CLK_FIRC>;
+ assigned-clocks-parents = <&clks IMX7ULP_CLK_FIRC_BUS_CLK>;
/*
* As the 1KHz LPO clock rate is not trimed,the actually clock
* is about 667Hz, so the init timeout 60s should set 40*1000
interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX7ULP_CLK_WDG2>;
assigned-clocks = <&clks IMX7ULP_CLK_WDG2>;
- assigned-clocks-parents = <&clks IMX7ULP_CLK_FIRC>;
+ assigned-clocks-parents = <&clks IMX7ULP_CLK_FIRC_BUS_CLK>;
timeout-sec = <40>;
};
#clock-cells = <1>;
assigned-clocks = <&clks IMX7ULP_CLK_LPTPM5>,
<&clks IMX7ULP_CLK_USDHC1>;
- assigned-clock-parents = <&clks IMX7ULP_CLK_SOSC>,
+ assigned-clock-parents = <&clks IMX7ULP_CLK_SOSC_BUS_CLK>,
<&clks IMX7ULP_CLK_NIC1_DIV>;
};
<&clks IMX7ULP_CLK_NIC1_BUS_DIV>;
clock-names = "per", "ipg";
assigned-clocks = <&clks IMX7ULP_CLK_LPI2C6>;
- assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>;
+ assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC_BUS_CLK>;
assigned-clock-rates = <48000000>;
status = "disabled";
};
<&clks IMX7ULP_CLK_NIC1_BUS_DIV>;
clock-names = "per", "ipg";
assigned-clocks = <&clks IMX7ULP_CLK_LPI2C7>;
- assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>;
+ assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC_BUS_CLK>;
assigned-clock-rates = <48000000>;
status = "disabled";
};
clocks = <&clks IMX7ULP_CLK_LPUART6>;
clock-names = "ipg";
assigned-clocks = <&clks IMX7ULP_CLK_LPUART6>;
- assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>;
+ assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC_BUS_CLK>;
assigned-clock-rates = <48000000>;
dmas = <&edma0 0 22>, <&edma0 0 21>;
dma-names = "tx","rx";
clocks = <&clks IMX7ULP_CLK_LPUART7>;
clock-names = "ipg";
assigned-clocks = <&clks IMX7ULP_CLK_LPUART7>;
- assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>;
+ assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC_BUS_CLK>;
assigned-clock-rates = <48000000>;
dmas = <&edma0 0 24>, <&edma0 0 23>;
dma-names = "tx","rx";
static const char *ddr_sels[] = { "apll_pfd_sel", "upll", };
static const char *nic_sels[] = { "firc", "ddr_div", };
static const char *periph_plat_sels[] = { "dummy", "nic1_bus", "nic1_div", "ddr_div", "apll_pfd2", "apll_pfd1", "apll_pfd0", "upll", };
-/* the dummy in only a space holder of spll_bus clk */
-static const char *periph_bus_sels[] = { "dummy", "sosc", "dummy", "firc", "rosc", "nic1_bus", "nic1_div", "dummy", };
+static const char *periph_bus_sels[] = { "dummy", "sosc_bus_clk", "dummy", "firc_bus_clk", "rosc", "nic1_bus", "nic1_div", "spll_bus_clk", };
static struct clk *clks[IMX7ULP_CLK_END];
static struct clk_onecell_data clk_data;