MLK-16986-5: drm: mxsfb_crtc: Fix the framebuffer misplacement

Currently the framebuffer content is displayed with incorrect offsets
in both the vertical and horizontal directions.

The fbdev version of the driver does not show this problem. Breno Lima
dumped the eLCDIF controller registers on both the drm and fbdev drivers
and noticed that the VDCTRL3 register is configured incorrectly in the
drm driver.

The fbdev driver calculates the vertical and horizontal wait counts
of the VDCTRL3 register by doing: back porch + sync length.

Looking at the horizontal and vertical timing diagram from
include/drm/drm_modes.h this value corresponds to:

crtc_[hv]total - crtc_[hv]sync_start

So fix the VDCTRL3 register setting accordingly so that the eLCDIF
controller can properly show the framebuffer content in the correct
position.

Reported-by: Breno Lima <breno.lima@nxp.com>
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Tested-by: Breno Lima <breno.lima@nxp.com>
Tested-by: Marek Vasut <marex@denx.de>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Signed-off-by: Robert Chiras <robert.chiras@nxp.com>

diff --git a/drivers/gpu/drm/mxsfb/mxsfb_crtc.c b/drivers/gpu/drm/mxsfb/mxsfb_crtc.c
index 1ac0321..87c9ce5 100644 (file)
--- a/drivers/gpu/drm/mxsfb/mxsfb_crtc.c
+++ b/drivers/gpu/drm/mxsfb/mxsfb_crtc.c
@@ -178,8 +178,6 @@ static void mxsfb_crtc_mode_set_nofb(struct mxsfb_drm_private *mxsfb)
 {
        struct drm_display_mode *m = &mxsfb->pipe.crtc.state->adjusted_mode;
        const u32 bus_flags = mxsfb->connector->display_info.bus_flags;
-       u32 hbp = m->crtc_hblank_end - m->crtc_hsync_end;
-       u32 vbp = m->crtc_vblank_end - m->crtc_vsync_end;
        u32 vdctrl0, vsync_pulse_len, hsync_pulse_len;
        int err;
 
@@ -243,8 +241,8 @@ static void mxsfb_crtc_mode_set_nofb(struct mxsfb_drm_private *mxsfb)
               VDCTRL2_SET_HSYNC_PERIOD(m->crtc_htotal),
               mxsfb->base + LCDC_VDCTRL2);
 
-       writel(SET_HOR_WAIT_CNT(hbp + hsync_pulse_len) |
-              SET_VERT_WAIT_CNT(vbp + vsync_pulse_len),
+       writel(SET_HOR_WAIT_CNT(m->crtc_htotal - m->crtc_hsync_start) |
+              SET_VERT_WAIT_CNT(m->crtc_vtotal - m->crtc_vsync_start),
               mxsfb->base + LCDC_VDCTRL3);
 
        writel(SET_DOTCLK_H_VALID_DATA_CNT(m->hdisplay),