--- /dev/null
+/*
+ * Copyright 2017 NXP
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/dts-v1/;
+
+/* First 128KB is for PSCI ATF. */
+/* Last 127M is for M4/RPMSG */
+/memreserve/ 0x80000000 0x08000000;
+
+#include "fsl-imx8qxp.dtsi"
+
+/ {
+ model = "Freescale i.MX8QXP MEK";
+ compatible = "fsl,imx8qxp-mek", "fsl,imx8qxp";
+
+ chosen {
+ bootargs = "console=ttyLP0,115200 earlycon=lpuart32,0x5a060000,115200";
+ stdout-path = &lpuart0;
+ };
+
+ regulators {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg_usdhc2_vmmc: usdhc2_vmmc {
+ compatible = "regulator-fixed";
+ regulator-name = "SD1_SPWR";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ gpio = <&gpio4 19 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ };
+};
+
+&iomuxc {
+ pinctrl-names = "default";
+ imx8qxp-mek {
+
+ pinctrl_lpuart0: lpuart0grp {
+ fsl,pins = <
+ SC_P_UART0_RX_ADMA_UART0_RX 0x0600004c
+ SC_P_UART0_TX_ADMA_UART0_TX 0x0600004c
+ >;
+ };
+
+ pinctrl_fec1: fec1grp {
+ fsl,pins = <
+ SC_P_ENET0_MDC_CONN_ENET0_MDC 0x06000048
+ SC_P_ENET0_MDIO_CONN_ENET0_MDIO 0x06000048
+ SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x06000048
+ SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x06000048
+ SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x06000048
+ SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x06000048
+ SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x06000048
+ SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x06000048
+ SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x06000048
+ SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x06000048
+ SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x06000048
+ SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x06000048
+ SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x06000048
+ SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x06000048
+ >;
+ };
+
+ pinctrl_usdhc1: usdhc1grp {
+ fsl,pins = <
+ SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041
+ SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021
+ SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021
+ SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021
+ SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021
+ SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021
+ SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021
+ SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021
+ SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021
+ SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021
+ SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x06000041
+ >;
+ };
+
+ pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
+ fsl,pins = <
+ SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000045
+ SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000025
+ SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000025
+ SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000025
+ SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000025
+ SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000025
+ SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000025
+ SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000025
+ SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000025
+ SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000025
+ SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x06000045
+ >;
+ };
+
+ pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
+ fsl,pins = <
+ SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000047
+ SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000027
+ SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000027
+ SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000027
+ SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000027
+ SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000027
+ SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000027
+ SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000027
+ SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000027
+ SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000027
+ SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x06000047
+ >;
+ };
+
+ pinctrl_usdhc2_gpio: usdhc2gpiogrp {
+ fsl,pins = <
+ SC_P_USDHC1_RESET_B_LSIO_GPIO4_IO19 0x06000048
+ SC_P_USDHC1_WP_LSIO_GPIO4_IO21 0x06000021
+ SC_P_USDHC1_CD_B_LSIO_GPIO4_IO22 0x06000021
+ >;
+ };
+
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <
+ SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041
+ SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x06000021
+ SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x06000021
+ SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x06000021
+ SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x06000021
+ SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x06000021
+ SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x06000021
+ >;
+ };
+
+ pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
+ fsl,pins = <
+ SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000045
+ SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x06000025
+ SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x06000025
+ SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x06000025
+ SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x06000025
+ SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x06000025
+ SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x06000021
+ >;
+ };
+
+ pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
+ fsl,pins = <
+ SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000047
+ SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x06000027
+ SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x06000027
+ SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x06000027
+ SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x06000027
+ SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x06000027
+ SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x06000021
+ >;
+ };
+ };
+};
+
+&lpuart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lpuart0>;
+ status = "okay";
+};
+
+&fec1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_fec1>;
+ phy-mode = "rgmii";
+ phy-handle = <ðphy0>;
+ fsl,ar8031-phy-fixup;
+ fsl,magic-packet;
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy0: ethernet-phy@0 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0>;
+ };
+
+ ethphy1: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+ };
+ };
+};
+
+&usdhc1 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc1>;
+ pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
+ bus-width = <8>;
+ non-removable;
+ status = "okay";
+};
+
+&usdhc2 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
+ bus-width = <4>;
+ cd-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
+ wp-gpios = <&gpio4 21 GPIO_ACTIVE_HIGH>;
+ vmmc-supply = <®_usdhc2_vmmc>;
+ status = "okay";
+};
projects / linux.git / commitdiff