void mxc_isi_cap_frame_write_done(struct mxc_isi_dev *mxc_isi)
{
+ struct device *dev = &mxc_isi->pdev->dev;
struct mxc_isi_buffer *buf;
struct vb2_buffer *vb2;
buf = list_first_entry(&mxc_isi->isi_cap.out_active,
struct mxc_isi_buffer, list);
+ /*
+ * Skip frame when buffer number is not match ISI trigger
+ * buffer
+ */
+ if (((mxc_isi->status & 0x100) && (buf->id == MXC_ISI_BUF2)) ||
+ ((mxc_isi->status & 0x200) && (buf->id == MXC_ISI_BUF1))) {
+ dev_dbg(dev, "status=0x%x id=%d\n", mxc_isi->status, buf->id);
+ return;
+ }
+
if (buf->discard) {
list_move_tail(mxc_isi->isi_cap.out_active.next,
&mxc_isi->isi_cap.out_discard);
if (list_empty(&mxc_isi->isi_cap.out_pending)) {
if (list_empty(&mxc_isi->isi_cap.out_discard)) {
- dev_warn(&mxc_isi->pdev->dev,
- "%s: trying to access empty discard list\n", __func__);
+ dev_warn(dev, "%s: trying to access empty discard list\n", __func__);
return;
}
status = mxc_isi_get_irq_status(mxc_isi);
mxc_isi_clean_irq_status(mxc_isi, status);
+ mxc_isi->status = status;
if (status & CHNL_STS_FRM_STRD_MASK) {
if (mxc_isi->is_m2m)
MXC_ISI_M2M_IN_FMT_YUV422_1P10P,
};
+enum mxc_isi_buf_id {
+ MXC_ISI_BUF1 = 0x0,
+ MXC_ISI_BUF2,
+};
+
struct mxc_isi_fmt {
char *name;
u32 mbus_code;
struct vb2_v4l2_buffer v4l2_buf;
struct list_head list;
struct frame_addr paddr;
+ enum mxc_isi_buf_id id;
bool discard;
};
u32 skip_m2m;
u32 req_cap_buf_num;
u32 req_out_buf_num;
+ u32 status;
u8 chain_buf;
atomic_t open_count;
}
val = readl(mxc_isi->regs + CHNL_OUT_BUF_CTRL);
-
- if (framecount % 2 == 0) {
+ if (framecount == 0 || ((mxc_isi->status & 0x100) && (framecount != 1))) {
writel(paddr->y, mxc_isi->regs + CHNL_OUT_BUF1_ADDR_Y);
writel(paddr->cb, mxc_isi->regs + CHNL_OUT_BUF1_ADDR_U);
writel(paddr->cr, mxc_isi->regs + CHNL_OUT_BUF1_ADDR_V);
val ^= CHNL_OUT_BUF_CTRL_LOAD_BUF1_ADDR_MASK;
- } else if (framecount % 2 == 1) {
+ buf->id = MXC_ISI_BUF1;
+ } else if (framecount == 1 || mxc_isi->status & 0x200) {
writel(paddr->y, mxc_isi->regs + CHNL_OUT_BUF2_ADDR_Y);
writel(paddr->cb, mxc_isi->regs + CHNL_OUT_BUF2_ADDR_U);
writel(paddr->cr, mxc_isi->regs + CHNL_OUT_BUF2_ADDR_V);
val ^= CHNL_OUT_BUF_CTRL_LOAD_BUF2_ADDR_MASK;
+ buf->id = MXC_ISI_BUF2;
}
writel(val, mxc_isi->regs + CHNL_OUT_BUF_CTRL);
}