MLK-13441-12 pinctrl: pinctrl-imx: add property to define mux register mask bits

Add property to define mux register mask bits when SHARE_MUX_CONF_REG
flag is added.

Signed-off-by: Fugang Duan <fugang.duan@nxp.com>

diff --git a/arch/arm/boot/dts/vfxxx.dtsi b/arch/arm/boot/dts/vfxxx.dtsi
index 2c13ec6..c96dd75 100644 (file)
--- a/arch/arm/boot/dts/vfxxx.dtsi
+++ b/arch/arm/boot/dts/vfxxx.dtsi
@@ -344,6 +344,7 @@
                        iomuxc: iomuxc@40048000 {
                                compatible = "fsl,vf610-iomuxc";
                                reg = <0x40048000 0x1000>;
+                               fsl,mux_mask = 0x700000;
                        };
 
                        gpio0: gpio@40049000 {

diff --git a/drivers/pinctrl/freescale/pinctrl-imx.c b/drivers/pinctrl/freescale/pinctrl-imx.c
index 7807e11..da8399b 100644 (file)
--- a/drivers/pinctrl/freescale/pinctrl-imx.c
+++ b/drivers/pinctrl/freescale/pinctrl-imx.c
@@ -204,6 +204,7 @@ static int imx_pmx_set(struct pinctrl_dev *pctldev, unsigned selector,
 
        for (i = 0; i < npins; i++) {
                struct imx_pin *pin = &grp->pins[i];
+               u32 mux_shift = info->mux_mask ? ffs(info->mux_mask) - 1 : 0;
                pin_id = pin->pin;
                pin_reg = &info->pin_regs[pin_id];
 
@@ -216,8 +217,8 @@ static int imx_pmx_set(struct pinctrl_dev *pctldev, unsigned selector,
                if (info->flags & SHARE_MUX_CONF_REG) {
                        u32 reg;
                        reg = readl(ipctl->base + pin_reg->mux_reg);
-                       reg &= ~(0x7 << 20);
-                       reg |= (pin->mux_mode << 20);
+                       reg &= ~info->mux_mask;
+                       reg |= (pin->mux_mode << mux_shift);
                        writel(reg, ipctl->base + pin_reg->mux_reg);
                } else {
                        writel(pin->mux_mode, ipctl->base + pin_reg->mux_reg);
@@ -335,7 +336,7 @@ static int imx_pmx_gpio_request_enable(struct pinctrl_dev *pctldev,
 
 mux_pin:
        reg = readl(ipctl->base + pin_reg->mux_reg);
-       reg &= ~(0x7 << 20);
+       reg &= ~info->mux_mask;
        reg |= imx_pin->config;
        writel(reg, ipctl->base + pin_reg->mux_reg);
 
@@ -754,6 +755,9 @@ int imx_pinctrl_probe(struct platform_device *pdev,
        if (IS_ERR(ipctl->base))
                return PTR_ERR(ipctl->base);
 
+       /* only for share mux and conf reg */
+       of_property_read_u32(dev_np, "fsl,mux_mask", &info->mux_mask);
+
        if (of_property_read_bool(dev_np, "fsl,input-sel")) {
                np = of_parse_phandle(dev_np, "fsl,input-sel", 0);
                if (!np) {

diff --git a/drivers/pinctrl/freescale/pinctrl-imx.h b/drivers/pinctrl/freescale/pinctrl-imx.h
index 0a18665..aff5434 100644 (file)
--- a/drivers/pinctrl/freescale/pinctrl-imx.h
+++ b/drivers/pinctrl/freescale/pinctrl-imx.h
@@ -83,6 +83,7 @@ struct imx_pinctrl_soc_info {
        unsigned int nfunctions;
        unsigned int flags;
        const char *gpr_compatible;
+       unsigned int mux_mask;
 };
 
 #define SHARE_MUX_CONF_REG     0x1