MLK-15289 imx8m: Change USDHC1/2 clocks to 200Mhz

The USDHC uses default clock root OSC 25Mhz, this causes SD/eMMC reading
very slowly.
This patch changes the USDHC IP/BUS clock to 200Mhz.

Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>

diff --git a/arch/arm/cpu/armv8/imx8m/clock.c b/arch/arm/cpu/armv8/imx8m/clock.c
index 17debd6..6e92863 100644 (file)
--- a/arch/arm/cpu/armv8/imx8m/clock.c
+++ b/arch/arm/cpu/armv8/imx8m/clock.c
@@ -551,9 +551,9 @@ int clock_init()
         */
        clock_enable(CCGR_USDHC1, 0);
        clock_enable(CCGR_USDHC2, 0);
-       clock_set_target_val(NAND_USDHC_BUS_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(0));
-       clock_set_target_val(USDHC1_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(0));
-       clock_set_target_val(USDHC2_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(0));
+       clock_set_target_val(NAND_USDHC_BUS_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(3));
+       clock_set_target_val(USDHC1_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(1) | CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2));
+       clock_set_target_val(USDHC2_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(1) | CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2));
        clock_enable(CCGR_USDHC1, 1);
        clock_enable(CCGR_USDHC2, 1);