MLK-14326-12 mx6sllevk: Update DTS files

Update i.MX6SLL dtsi file and mx6sll-evk DTS file to latest in kernel.

Signed-off-by: Ye Li <ye.li@nxp.com>

diff --git a/arch/arm/dts/imx6sll-evk.dts b/arch/arm/dts/imx6sll-evk.dts
index b4af007..f3a7fad 100644 (file)
--- a/arch/arm/dts/imx6sll-evk.dts
+++ b/arch/arm/dts/imx6sll-evk.dts
@@ -534,34 +534,34 @@
 
                pinctrl_usdhc1: usdhc1grp {
                        fsl,pins = <
-                               MX6SLL_PAD_SD1_CMD__SD1_CMD     0x17059
-                               MX6SLL_PAD_SD1_CLK__SD1_CLK     0x13059
-                               MX6SLL_PAD_SD1_DATA0__SD1_DATA0 0x17059
-                               MX6SLL_PAD_SD1_DATA1__SD1_DATA1 0x17059
-                               MX6SLL_PAD_SD1_DATA2__SD1_DATA2 0x17059
-                               MX6SLL_PAD_SD1_DATA3__SD1_DATA3 0x17059
+                               MX6SLL_PAD_SD1_CMD__SD1_CMD     0x17061
+                               MX6SLL_PAD_SD1_CLK__SD1_CLK     0x13061
+                               MX6SLL_PAD_SD1_DATA0__SD1_DATA0 0x17061
+                               MX6SLL_PAD_SD1_DATA1__SD1_DATA1 0x17061
+                               MX6SLL_PAD_SD1_DATA2__SD1_DATA2 0x17061
+                               MX6SLL_PAD_SD1_DATA3__SD1_DATA3 0x17061
                        >;
                };
 
                pinctrl_usdhc1_100mhz: usdhc1grp_100mhz {
                        fsl,pins = <
-                               MX6SLL_PAD_SD1_CMD__SD1_CMD     0x170b9
-                               MX6SLL_PAD_SD1_CLK__SD1_CLK     0x130b9
-                               MX6SLL_PAD_SD1_DATA0__SD1_DATA0 0x170b9
-                               MX6SLL_PAD_SD1_DATA1__SD1_DATA1 0x170b9
-                               MX6SLL_PAD_SD1_DATA2__SD1_DATA2 0x170b9
-                               MX6SLL_PAD_SD1_DATA3__SD1_DATA3 0x170b9
+                               MX6SLL_PAD_SD1_CMD__SD1_CMD     0x170a1
+                               MX6SLL_PAD_SD1_CLK__SD1_CLK     0x130a1
+                               MX6SLL_PAD_SD1_DATA0__SD1_DATA0 0x170a1
+                               MX6SLL_PAD_SD1_DATA1__SD1_DATA1 0x170a1
+                               MX6SLL_PAD_SD1_DATA2__SD1_DATA2 0x170a1
+                               MX6SLL_PAD_SD1_DATA3__SD1_DATA3 0x170a1
                        >;
                };
 
                pinctrl_usdhc1_200mhz: usdhc1grp_200mhz {
                        fsl,pins = <
-                               MX6SLL_PAD_SD1_CMD__SD1_CMD     0x170f9
+                               MX6SLL_PAD_SD1_CMD__SD1_CMD     0x170e9
                                MX6SLL_PAD_SD1_CLK__SD1_CLK     0x130f9
-                               MX6SLL_PAD_SD1_DATA0__SD1_DATA0 0x170f9
-                               MX6SLL_PAD_SD1_DATA1__SD1_DATA1 0x170f9
-                               MX6SLL_PAD_SD1_DATA2__SD1_DATA2 0x170f9
-                               MX6SLL_PAD_SD1_DATA3__SD1_DATA3 0x170f9
+                               MX6SLL_PAD_SD1_DATA0__SD1_DATA0 0x170e9
+                               MX6SLL_PAD_SD1_DATA1__SD1_DATA1 0x170e9
+                               MX6SLL_PAD_SD1_DATA2__SD1_DATA2 0x170e9
+                               MX6SLL_PAD_SD1_DATA3__SD1_DATA3 0x170e9
                        >;
                };
 
@@ -615,34 +615,34 @@
 
                pinctrl_usdhc3: usdhc3grp {
                        fsl,pins = <
-                               MX6SLL_PAD_SD3_CMD__SD3_CMD     0x17059
-                               MX6SLL_PAD_SD3_CLK__SD3_CLK     0x13059
-                               MX6SLL_PAD_SD3_DATA0__SD3_DATA0 0x17059
-                               MX6SLL_PAD_SD3_DATA1__SD3_DATA1 0x17059
-                               MX6SLL_PAD_SD3_DATA2__SD3_DATA2 0x17059
-                               MX6SLL_PAD_SD3_DATA3__SD3_DATA3 0x17059
+                               MX6SLL_PAD_SD3_CMD__SD3_CMD     0x17061
+                               MX6SLL_PAD_SD3_CLK__SD3_CLK     0x13061
+                               MX6SLL_PAD_SD3_DATA0__SD3_DATA0 0x17061
+                               MX6SLL_PAD_SD3_DATA1__SD3_DATA1 0x17061
+                               MX6SLL_PAD_SD3_DATA2__SD3_DATA2 0x17061
+                               MX6SLL_PAD_SD3_DATA3__SD3_DATA3 0x17061
                        >;
                };
 
                pinctrl_usdhc3_100mhz: usdhc3grp_100mhz {
                        fsl,pins = <
-                               MX6SLL_PAD_SD3_CMD__SD3_CMD     0x170b9
-                               MX6SLL_PAD_SD3_CLK__SD3_CLK     0x130b9
-                               MX6SLL_PAD_SD3_DATA0__SD3_DATA0 0x170b9
-                               MX6SLL_PAD_SD3_DATA1__SD3_DATA1 0x170b9
-                               MX6SLL_PAD_SD3_DATA2__SD3_DATA2 0x170b9
-                               MX6SLL_PAD_SD3_DATA3__SD3_DATA3 0x170b9
+                               MX6SLL_PAD_SD3_CMD__SD3_CMD     0x170a1
+                               MX6SLL_PAD_SD3_CLK__SD3_CLK     0x130a1
+                               MX6SLL_PAD_SD3_DATA0__SD3_DATA0 0x170a1
+                               MX6SLL_PAD_SD3_DATA1__SD3_DATA1 0x170a1
+                               MX6SLL_PAD_SD3_DATA2__SD3_DATA2 0x170a1
+                               MX6SLL_PAD_SD3_DATA3__SD3_DATA3 0x170a1
                        >;
                };
 
                pinctrl_usdhc3_200mhz: usdhc3grp_200mhz {
                        fsl,pins = <
-                               MX6SLL_PAD_SD3_CMD__SD3_CMD     0x170f9
+                               MX6SLL_PAD_SD3_CMD__SD3_CMD     0x170e9
                                MX6SLL_PAD_SD3_CLK__SD3_CLK     0x130f9
-                               MX6SLL_PAD_SD3_DATA0__SD3_DATA0 0x170f9
-                               MX6SLL_PAD_SD3_DATA1__SD3_DATA1 0x170f9
-                               MX6SLL_PAD_SD3_DATA2__SD3_DATA2 0x170f9
-                               MX6SLL_PAD_SD3_DATA3__SD3_DATA3 0x170f9
+                               MX6SLL_PAD_SD3_DATA0__SD3_DATA0 0x170e9
+                               MX6SLL_PAD_SD3_DATA1__SD3_DATA1 0x170e9
+                               MX6SLL_PAD_SD3_DATA2__SD3_DATA2 0x170e9
+                               MX6SLL_PAD_SD3_DATA3__SD3_DATA3 0x170e9
                        >;
                };
 
@@ -671,6 +671,12 @@
                                MX6SLL_PAD_PWM1__PWM1_OUT   0x110b0
                        >;
                };
+
+               pinctrl_wdog1: wdog1grp {
+                       fsl,pins = <
+                               MX6SLL_PAD_WDOG_B__WDOG1_B   0x170b0
+                       >;
+               };
        };
 };
 
@@ -799,3 +805,9 @@
 &ssi2 {
        status = "okay";
 };
+
+&wdog1 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_wdog1>;
+       fsl,wdog_b;
+};

diff --git a/arch/arm/dts/imx6sll.dtsi b/arch/arm/dts/imx6sll.dtsi
index 349c47a..79b8595 100644 (file)
--- a/arch/arm/dts/imx6sll.dtsi
+++ b/arch/arm/dts/imx6sll.dtsi
@@ -528,7 +528,6 @@
                                fsl,tempmon = <&anatop>;
                                fsl,tempmon-data = <&ocotp>;
                                clocks = <&clks IMX6SLL_CLK_PLL3_USB_OTG>;
-                               status = "disabled";
                        };
 
                        usbphy1: usbphy@020c9000 {
@@ -629,7 +628,7 @@
                        };
 
                        sdma: sdma@020ec000 {
-                               compatible = "fsl,imx6sll-sdma", "fsl,imx35-sdma";
+                               compatible = "fsl,imx6ul-sdma", "fsl,imx35-sdma";
                                reg = <0x020ec000 0x4000>;
                                interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&clks IMX6SLL_CLK_SDMA>,
@@ -679,7 +678,7 @@
                                             <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&clks IMX6SLL_CLK_DCP>;
                                clock-names = "dcp";
-                       };
+                       }; 
                };
 
                aips2: aips-bus@02100000 {
@@ -726,7 +725,7 @@
                        };
 
                        usdhc1: usdhc@02190000 {
-                               compatible = "fsl,imx6sll-usdhc", "fsl,imx6sx-usdhc";
+                               compatible = "fsl,imx6sll-usdhc", "fsl,imx7d-usdhc";
                                reg = <0x02190000 0x4000>;
                                interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&clks IMX6SLL_CLK_USDHC1>,
@@ -740,7 +739,7 @@
                        };
 
                        usdhc2: usdhc@02194000 {
-                               compatible = "fsl,imx6sll-usdhc", "fsl,imx6sx-usdhc";
+                               compatible = "fsl,imx6sll-usdhc", "fsl,imx7d-usdhc";
                                reg = <0x02194000 0x4000>;
                                interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&clks IMX6SLL_CLK_USDHC2>,
@@ -754,7 +753,7 @@
                        };
 
                        usdhc3: usdhc@02198000 {
-                               compatible = "fsl,imx6sll-usdhc", "fsl,imx6sx-usdhc";
+                               compatible = "fsl,imx6sll-usdhc", "fsl,imx7d-usdhc";
                                reg = <0x02198000 0x4000>;
                                interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&clks IMX6SLL_CLK_USDHC3>,