ARM: dts: STiH410-family: fix wrong parent clock frequency

[ Upstream commit b9ec866d223f38eb0bf2a7c836e10031ee17f7af ]

The clock parent was lower than child clock which is not correct.
In some use case, it leads to division by zero.

Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
Signed-off-by: Sasha Levin <alexander.levin@verizon.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

diff --git a/arch/arm/boot/dts/stih410.dtsi b/arch/arm/boot/dts/stih410.dtsi
index a3ef734..4d329b2 100644 (file)
--- a/arch/arm/boot/dts/stih410.dtsi
+++ b/arch/arm/boot/dts/stih410.dtsi
@@ -131,7 +131,7 @@
                                                 <&clk_s_d2_quadfs 0>;
 
                        assigned-clock-rates = <297000000>,
-                                              <108000000>,
+                                              <297000000>,
                                               <0>,
                                               <400000000>,
                                               <400000000>;