MLK-11284 ARM: ERRATA: Add ARM/MP: 814220 SW workaround

ARM/MP: 814220—B-Cache maintenance by set/way operations can execute out of order.

Description:
The v7 ARM states that all cache and branch predictor maintenance operations
that do not specify an address execute, relative to each other, in program
order. However, because of this erratum, an L2 set/way cache maintenance
operation can overtake an L1 set/way cache maintenance operation, this would
cause the data corruption.

This ERRATA affected the Cortex-A7 and present in r0p2, r0p3, r0p4, r0p5.

This patch is the SW workaround by adding a DSB before changing cache levels as
the ARM ERRATA: ARM/MP: 814220 told in the ARM ERRATA documentation.

Signed-off-by: Jason Liu <r64343@freescale.com>
(cherry picked from commit 0e9a87bbd4f7d1c48e42c65aa94939a7283599dd)

Conflicts:
	arch/arm/mach-imx/Kconfig

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index c2c49f6..52af0ba 100644 (file)
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1206,6 +1206,16 @@ config ARM_ERRATA_825619
          DMB NSHST or DMB ISHST instruction followed by a mix of Cacheable
          and Device/Strongly-Ordered loads and stores might cause deadlock
 
+config ARM_ERRATA_814220
+       bool "ARM errata: Cache maintenance by set/way operations can execute out of order"
+       depends on CPU_V7
+       help
+         The v7 ARM states that all cache and branch predictor maintenance operations
+         that do not specify an address execute, relative to each other, in program order.
+         However, because of this erratum, an L2 set/way cache maintenance operation can
+         overtake an L1 set/way cache maintenance operation. This ERRATA only affected the
+         Cortex-A7 and present in r0p2, r0p3, r0p4, r0p5.
+
 config ARM_ERRATA_852421
        bool "ARM errata: A17: DMB ST might fail to create order between stores"
        depends on CPU_V7

diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 7a1cb6e..c05bc20 100644 (file)
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -549,6 +549,7 @@ config SOC_IMX6UL
        select PINCTRL_IMX6UL
        select SOC_IMX6
        select KEYBOARD_SNVS_PWRKEY
+       select ARM_ERRATA_814220
 
        help
          This enables support for Freescale i.MX6 UltraLite processor.
@@ -568,6 +569,7 @@ config SOC_IMX7D
        select KEYBOARD_SNVS_PWRKEY
        select HAVE_IMX_GPCV2
        select CPU_V7
+       select ARM_ERRATA_814220
 
        help
                This enables support for Freescale i.MX7 Dual processor.

diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S
index a134d8a..d2dd211 100644 (file)
--- a/arch/arm/mm/cache-v7.S
+++ b/arch/arm/mm/cache-v7.S
@@ -162,6 +162,9 @@ loop2:
 skip:
        add     r10, r10, #2                    @ increment cache number
        cmp     r3, r10
+#ifdef CONFIG_ARM_ERRATA_814220
+       dsb
+#endif
        bgt     flush_levels
 finished:
        mov     r10, #0                         @ swith back to cache level 0