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MLK-18101-2 arm64: dtsi: fsl-imx8qxp: Add prg1 for dpr1_channel2
authorYuchou Gan <yuchou.gan@nxp.com>
Fri, 20 Apr 2018 15:15:50 +0000 (23:15 +0800)
committerYuchou Gan <yuchou.gan@nxp.com>
Fri, 27 Apr 2018 10:00:11 +0000 (18:00 +0800)
On QXP B0 board, prg1 can alternative connect to
dpr_channel1 and channel2. And if enable PRG0_SEL:BLIT0,
prg1 will connect to channel2, so it could
support 2-plane format tile to linear convert.

Signed-off-by: yuchou gan <yuchou.gan@nxp.com>
arch/arm64/boot/dts/freescale/fsl-imx8qxp.dtsi patch | blob | history

diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8qxp.dtsi
index e9f1cb4..36b3055 100644 (file)
--- a/arch/arm64/boot/dts/freescale/fsl-imx8qxp.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-imx8qxp.dtsi
@@ -1183,7 +1183,7 @@
                             "fsl,imx8qm-dpr-channel";
                reg = <0x0 0x560e0000 0x0 0x10000>;
                fsl,sc-resource = <SC_R_DC_0_BLIT1>;
-               fsl,prgs = <&prg2>;
+               fsl,prgs = <&prg2>, <&prg1>;
                clocks = <&clk IMX8QXP_DC0_DPR0_APB_CLK>,
                         <&clk IMX8QXP_DC0_DPR0_B_CLK>,
                         <&clk IMX8QXP_DC0_RTRAM0_CLK>;