arm64: dts: imx8mp-evk: enable uart1/3 ports

Enable uart1/3 ports for evk board.

Reviewed-by: Robin Gong <yibin.gong@nxp.com>
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>

diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
index 9b2a75b..af04072 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
@@ -572,6 +572,15 @@
        status = "okay";
 };
 
+&uart1 { /* BT */
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_uart1>;
+       assigned-clocks = <&clk IMX8MP_CLK_UART1>;
+       assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>;
+       fsl,uart-has-rtscts;
+       status = "okay";
+};
+
 &uart2 {
        /* console */
        pinctrl-names = "default";
@@ -579,6 +588,15 @@
        status = "okay";
 };
 
+&uart3 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_uart3>;
+       assigned-clocks = <&clk IMX8MP_CLK_UART3>;
+       assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>;
+       fsl,uart-has-rtscts;
+       status = "okay";
+};
+
 &usdhc2 {
        assigned-clocks = <&clk IMX8MP_CLK_USDHC2>;
        assigned-clock-rates = <400000000>;
@@ -786,6 +804,15 @@
                >;
        };
 
+       pinctrl_uart1: uart1grp {
+               fsl,pins = <
+                       MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX    0x140
+                       MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX    0x140
+                       MX8MP_IOMUXC_UART3_RXD__UART1_DCE_CTS   0x140
+                       MX8MP_IOMUXC_UART3_TXD__UART1_DCE_RTS   0x140
+               >;
+       };
+
        pinctrl_uart2: uart2grp {
                fsl,pins = <
                        MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX    0x49
@@ -793,6 +820,15 @@
                >;
        };
 
+       pinctrl_uart3: uart3grp {
+               fsl,pins = <
+                       MX8MP_IOMUXC_ECSPI1_SCLK__UART3_DCE_RX          0x140
+                       MX8MP_IOMUXC_ECSPI1_MOSI__UART3_DCE_TX          0x140
+                       MX8MP_IOMUXC_ECSPI1_SS0__UART3_DCE_RTS          0x140
+                       MX8MP_IOMUXC_ECSPI1_MISO__UART3_DCE_CTS         0x140
+               >;
+       };
+
        pinctrl_usdhc2: usdhc2grp {
                fsl,pins = <
                        MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK        0x190