igc: Remove Sequence Error Counter
authorSasha Neftin <sasha.neftin@intel.com>
Thu, 28 May 2020 07:11:11 +0000 (10:11 +0300)
committerJeff Kirsher <jeffrey.t.kirsher@intel.com>
Fri, 29 May 2020 03:32:04 +0000 (20:32 -0700)
Accordance to the i225 datasheet sequence error counter does not
applicable to the i225 device.
This patch comes to clean up this counter.

Signed-off-by: Sasha Neftin <sasha.neftin@intel.com>
Tested-by: Aaron Brown <aaron.f.brown@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
drivers/net/ethernet/intel/igc/igc_mac.c
drivers/net/ethernet/intel/igc/igc_main.c
drivers/net/ethernet/intel/igc/igc_regs.h

index a5a087e..fb49661 100644 (file)
@@ -243,7 +243,6 @@ void igc_clear_hw_cntrs_base(struct igc_hw *hw)
        rd32(IGC_COLC);
        rd32(IGC_RERC);
        rd32(IGC_DC);
-       rd32(IGC_SEC);
        rd32(IGC_RLEC);
        rd32(IGC_XONRXC);
        rd32(IGC_XONTXC);
index e0c45ff..43fcabb 100644 (file)
@@ -3701,7 +3701,6 @@ void igc_update_stats(struct igc_adapter *adapter)
        adapter->stats.prc511 += rd32(IGC_PRC511);
        adapter->stats.prc1023 += rd32(IGC_PRC1023);
        adapter->stats.prc1522 += rd32(IGC_PRC1522);
-       adapter->stats.sec += rd32(IGC_SEC);
 
        mpc = rd32(IGC_MPC);
        adapter->stats.mpc += mpc;
index 7ac3b61..2b7a877 100644 (file)
 #define IGC_RERC       0x0402C  /* Receive Error Count - R/clr */
 #define IGC_DC         0x04030  /* Defer Count - R/clr */
 #define IGC_TNCRS      0x04034  /* Tx-No CRS - R/clr */
-#define IGC_SEC                0x04038  /* Sequence Error Count - R/clr */
 #define IGC_CEXTERR    0x0403C  /* Carrier Extension Error Count - R/clr */
 #define IGC_RLEC       0x04040  /* Receive Length Error Count - R/clr */
 #define IGC_XONRXC     0x04048  /* XON Rx Count - R/clr */