Remove get core clock rate code,
get cec clk div from HDMI SW_CLK_H register.
Signed-off-by: Sandor Yu <Sandor.yu@nxp.com>
#ifdef CONFIG_IMX_HDP_CEC
static void imx_hdp_cec_init(struct imx_hdp *hdp)
{
+ state_struct *state = &hdp->state;
struct imx_cec_dev *cec = &hdp->cec;
+ u32 clk_MHz;
memset(cec, 0, sizeof(struct imx_cec_dev));
- if (hdp->clks.clk_core)
- cec->clk_core = hdp->clks.clk_core;
+ CDN_API_GetClock(state, &clk_MHz);
+ cec->clk_div = clk_MHz * 10;
cec->dev = hdp->dev;
cec->mem = &hdp->mem;
cec->rw = hdp->rw;
struct device *dev = cec->dev;
int ret;
- /* Set CEC clock divider */
- if (cec->clk_core)
- cec->clk_div = clk_get_rate(cec->clk_core) / 100000;
- else
- /* Default HDMI core clock rate 133MHz */
- cec->clk_div = 1330;
-
cec->adap = cec_allocate_adapter(&imx_cec_adap_ops, cec,
CEC_NAME,
CEC_CAP_PHYS_ADDR | CEC_CAP_LOG_ADDRS |
struct task_struct *cec_worker;
/* inited by HDP controller driver */
- struct clk *clk_core;
struct hdp_mem *mem;
struct hdp_rw_func *rw;
};